Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3357267	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4093862

1

T1

1

T2

4584

T3

7523

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4030597	1			T1	49		T2	3549		T3	4403
values[0x0]	1708473	1			T2	2161		T3	2670		T4	460
values[0x1]	1712059	1			T2	2079		T3	2614		T4	438

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2383500	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5067629

1

T1

19

T2

5456

T3

7970

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30391	1			T2	37		T3	27		T6	43
valid_sources[0x01]	32742	1			T2	52		T3	25		T6	30
valid_sources[0x02]	27125	1			T2	35		T3	33		T6	24
valid_sources[0x03]	28128	1			T2	44		T3	33		T6	64
valid_sources[0x04]	29037	1			T2	21		T3	36		T6	38
valid_sources[0x05]	29408	1			T2	30		T3	48		T6	21
valid_sources[0x06]	33811	1			T2	40		T3	25		T6	42
valid_sources[0x07]	30532	1			T2	44		T3	33		T6	48
valid_sources[0x08]	27621	1			T2	63		T3	48		T6	35
valid_sources[0x09]	27610	1			T2	45		T3	29		T6	36
valid_sources[0x0a]	30978	1			T2	78		T3	38		T6	66
valid_sources[0x0b]	27210	1			T2	42		T3	33		T6	41
valid_sources[0x0c]	28997	1			T2	68		T3	29		T6	50
valid_sources[0x0d]	26659	1			T2	51		T3	31		T6	29
valid_sources[0x0e]	30297	1			T2	21		T3	21		T6	35
valid_sources[0x0f]	28801	1			T2	17		T3	38		T6	50
valid_sources[0x10]	27926	1			T2	26		T3	34		T6	57
valid_sources[0x11]	26300	1			T3	35		T6	33		T7	35
valid_sources[0x12]	27512	1			T2	26		T3	38		T6	37
valid_sources[0x13]	26622	1			T2	19		T3	28		T6	45
valid_sources[0x14]	30641	1			T2	18		T3	16		T6	59
valid_sources[0x15]	28437	1			T2	22		T3	28		T6	36
valid_sources[0x16]	29788	1			T2	49		T3	33		T6	50
valid_sources[0x17]	29499	1			T2	28		T3	45		T6	45
valid_sources[0x18]	27584	1			T2	10		T3	44		T6	43
valid_sources[0x19]	29004	1			T2	27		T3	47		T6	22
valid_sources[0x1a]	31441	1			T2	5		T3	31		T6	40
valid_sources[0x1b]	28669	1			T2	21		T3	27		T6	62
valid_sources[0x1c]	30190	1			T2	30		T3	31		T6	39
valid_sources[0x1d]	28864	1			T2	32		T3	33		T6	54
valid_sources[0x1e]	30812	1			T2	34		T3	49		T6	37
valid_sources[0x1f]	29758	1			T2	21		T3	42		T6	31
valid_sources[0x20]	29376	1			T2	28		T3	52		T6	38
valid_sources[0x21]	26244	1			T2	34		T3	51		T6	39
valid_sources[0x22]	31295	1			T2	14		T3	37		T4	558
valid_sources[0x23]	28496	1			T2	20		T3	26		T6	28
valid_sources[0x24]	34816	1			T2	13		T3	48		T6	32
valid_sources[0x25]	26679	1			T2	20		T3	58		T6	28
valid_sources[0x26]	28601	1			T2	42		T3	36		T6	39
valid_sources[0x27]	28024	1			T2	3		T3	58		T6	51
valid_sources[0x28]	27470	1			T2	18		T3	31		T6	41
valid_sources[0x29]	28560	1			T2	38		T3	35		T6	50
valid_sources[0x2a]	27547	1			T2	26		T3	47		T6	33
valid_sources[0x2b]	29528	1			T2	22		T3	41		T6	41
valid_sources[0x2c]	27450	1			T2	45		T3	44		T6	27
valid_sources[0x2d]	26920	1			T2	53		T3	45		T6	42
valid_sources[0x2e]	28238	1			T2	26		T3	32		T6	43
valid_sources[0x2f]	30675	1			T2	36		T3	32		T6	58
valid_sources[0x30]	35212	1			T2	32		T3	33		T6	48
valid_sources[0x31]	27086	1			T2	27		T3	39		T6	47
valid_sources[0x32]	25974	1			T2	21		T3	39		T6	41
valid_sources[0x33]	57740	1			T2	18		T3	31		T6	50
valid_sources[0x34]	26907	1			T2	26		T3	27		T6	42
valid_sources[0x35]	26558	1			T2	21		T3	55		T6	26
valid_sources[0x36]	29711	1			T2	35		T3	26		T6	42
valid_sources[0x37]	28605	1			T2	52		T3	48		T6	34
valid_sources[0x38]	27707	1			T2	7		T3	37		T6	34
valid_sources[0x39]	26278	1			T2	4		T3	52		T6	56
valid_sources[0x3a]	27199	1			T2	3		T3	44		T6	38
valid_sources[0x3b]	28386	1			T2	37		T3	30		T6	37
valid_sources[0x3c]	35321	1			T2	35		T3	45		T6	63
valid_sources[0x3d]	27528	1			T2	51		T3	26		T6	57
valid_sources[0x3e]	27898	1			T2	37		T3	40		T6	53
valid_sources[0x3f]	26652	1			T2	7		T3	32		T6	56
valid_sources[0x40]	28202	1			T2	39		T3	29		T6	28
valid_sources[0x41]	32364	1			T2	26		T3	48		T6	39
valid_sources[0x42]	26938	1			T2	27		T3	26		T6	46
valid_sources[0x43]	27245	1			T2	14		T3	50		T6	33
valid_sources[0x44]	27877	1			T2	33		T3	31		T6	30
valid_sources[0x45]	27543	1			T2	18		T3	33		T6	41
valid_sources[0x46]	27087	1			T2	25		T3	33		T4	416
valid_sources[0x47]	25998	1			T2	5		T3	39		T6	44
valid_sources[0x48]	29192	1			T2	52		T3	36		T6	44
valid_sources[0x49]	29463	1			T2	21		T3	34		T6	41
valid_sources[0x4a]	27420	1			T2	38		T3	33		T6	52
valid_sources[0x4b]	28618	1			T2	26		T3	35		T6	56
valid_sources[0x4c]	37096	1			T2	42		T3	27		T6	47
valid_sources[0x4d]	27883	1			T2	43		T3	31		T6	33
valid_sources[0x4e]	28346	1			T2	18		T3	27		T6	32
valid_sources[0x4f]	26613	1			T2	41		T3	49		T6	56
valid_sources[0x50]	26980	1			T2	21		T3	39		T6	39
valid_sources[0x51]	28759	1			T2	28		T3	26		T6	43
valid_sources[0x52]	26773	1			T2	21		T3	30		T6	51
valid_sources[0x53]	37626	1			T2	51		T3	60		T6	29
valid_sources[0x54]	28792	1			T2	11		T3	52		T6	42
valid_sources[0x55]	27691	1			T2	20		T3	34		T6	40
valid_sources[0x56]	26569	1			T2	8		T3	39		T6	33
valid_sources[0x57]	37468	1			T2	17		T3	39		T6	31
valid_sources[0x58]	28725	1			T2	12		T3	43		T6	60
valid_sources[0x59]	29729	1			T2	36		T3	41		T6	31
valid_sources[0x5a]	29117	1			T2	30		T3	39		T6	47
valid_sources[0x5b]	26710	1			T2	16		T3	40		T6	44
valid_sources[0x5c]	30221	1			T2	4		T3	42		T6	40
valid_sources[0x5d]	29594	1			T2	6		T3	35		T6	45
valid_sources[0x5e]	27504	1			T2	9		T3	40		T6	47
valid_sources[0x5f]	28190	1			T2	18		T3	55		T6	30
valid_sources[0x60]	29227	1			T2	24		T3	35		T6	67
valid_sources[0x61]	30698	1			T2	50		T3	35		T6	43
valid_sources[0x62]	27266	1			T2	40		T3	50		T6	34
valid_sources[0x63]	28276	1			T2	20		T3	49		T6	51
valid_sources[0x64]	29303	1			T2	2		T3	39		T6	35
valid_sources[0x65]	34020	1			T2	13		T3	31		T6	47
valid_sources[0x66]	26836	1			T2	1		T3	31		T6	35
valid_sources[0x67]	29786	1			T2	43		T3	32		T6	44
valid_sources[0x68]	25247	1			T2	33		T3	41		T6	61
valid_sources[0x69]	48800	1			T2	71		T3	51		T6	30
valid_sources[0x6a]	33094	1			T2	43		T3	39		T6	45
valid_sources[0x6b]	25430	1			T2	32		T3	33		T6	48
valid_sources[0x6c]	27111	1			T2	47		T3	36		T6	60
valid_sources[0x6d]	27386	1			T2	40		T3	29		T6	29
valid_sources[0x6e]	31037	1			T2	22		T3	48		T6	39
valid_sources[0x6f]	26442	1			T2	27		T3	41		T6	39
valid_sources[0x70]	29744	1			T2	51		T3	53		T6	41
valid_sources[0x71]	31389	1			T2	12		T3	30		T6	51
valid_sources[0x72]	26262	1			T2	24		T3	35		T6	60
valid_sources[0x73]	27086	1			T2	36		T3	27		T6	45
valid_sources[0x74]	30616	1			T2	16		T3	51		T6	49
valid_sources[0x75]	28629	1			T2	33		T3	39		T6	43
valid_sources[0x76]	27437	1			T2	26		T3	29		T6	38
valid_sources[0x77]	26973	1			T2	12		T3	32		T6	68
valid_sources[0x78]	27644	1			T2	50		T3	31		T6	30
valid_sources[0x79]	27757	1			T2	23		T3	34		T6	46
valid_sources[0x7a]	32603	1			T2	25		T3	43		T6	61
valid_sources[0x7b]	27669	1			T2	8		T3	41		T6	41
valid_sources[0x7c]	29317	1			T2	8		T3	23		T6	61
valid_sources[0x7d]	28310	1			T2	37		T3	47		T6	48
valid_sources[0x7e]	34849	1			T2	20		T3	29		T6	45
valid_sources[0x7f]	27260	1			T2	63		T3	60		T6	47
valid_sources[0x80]	28226	1			T2	16		T3	43		T4	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

983559

1

T1

1

T2

1338

T3

2268

values[0x0]

all_enables

biggest_size

1565495

1

T2

1684

T3

2660

T4

456

values[0x1]

all_enables

biggest_size

1544808

1

T2

1562

T3

2595

T4

432