Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3377101

1

T1

48

T2

3205

T3

2164

full_word

4095001

1

T1

1

T2

4584

T3

7523

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7471712	1			T1	49		T2	7789		T3	9687
auto[TlIntgErrCmd]	131	1			T84	5		T86	9		T87	3
auto[TlIntgErrData]	121	1			T84	6		T86	11		T87	4
auto[TlIntgErrBoth]	138	1			T84	9		T86	10		T87	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4033638

1

T1

49

T2

3549

T3

4403

auto[1]

3438464

1

T2

4240

T3

5284

T4

898

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3049665	1			T1	48		T2	2211		T3	2135
auto[TlIntgErrNone]	partial	auto[1]	327088	1			T2	994		T3	29		T4	10
auto[TlIntgErrNone]	full_word	auto[0]	983808	1			T1	1		T2	1338		T3	2268
auto[TlIntgErrNone]	full_word	auto[1]	3111151	1			T2	3246		T3	5255		T4	888
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T84	2		T86	4		T142	4
auto[TlIntgErrCmd]	partial	auto[1]	76	1			T84	2		T86	5		T87	3
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T170	1		T165	1		T171	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T84	1		T171	1		T169	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T86	5		T87	3		T142	5
auto[TlIntgErrData]	partial	auto[1]	59	1			T84	6		T86	4		T87	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T86	2		T172	1		T166	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T142	1		T166	1		T173	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T84	5		T86	4		T87	3
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T84	3		T86	4		T142	6
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T86	1		T142	1		T168	2
auto[TlIntgErrBoth]	full_word	auto[1]	11	1			T84	1		T86	1		T142	1