Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T3,T4,T6
1	0	Covered	T3,T4,T6
1	1	Covered	T3,T4,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T6
1	0	Covered	T3,T4,T6
1	1	Covered	T3,T4,T6

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1320229068	2691	0	0
SrcPulseCheck_M	446654013	2691	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1320229068	2691	0	0
T3	298444	7	0	0
T4	132844	6	0	0
T6	0	13	0	0
T12	0	10	0	0
T16	82564	1	0	0
T17	38650	0	0	0
T18	448701	17	0	0
T24	7324	0	0	0
T25	3731	0	0	0
T26	93589	0	0	0
T27	427872	5	0	0
T28	411122	0	0	0
T37	240117	8	0	0
T38	323552	10	0	0
T39	175931	2	0	0
T40	15698	7	0	0
T41	0	2	0	0
T42	0	7	0	0
T43	80538	3	0	0
T62	726	0	0	0
T75	101167	0	0	0
T76	137544	0	0	0
T77	350387	0	0	0
T78	0	3	0	0
T101	179736	0	0	0
T134	0	7	0	0
T135	0	5	0	0
T136	0	7	0	0
T137	0	7	0	0
T138	0	7	0	0
T139	0	7	0	0
T140	1149	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446654013	2691	0	0
T3	490671	7	0	0
T4	40260	6	0	0
T6	0	13	0	0
T12	0	10	0	0
T16	32266	1	0	0
T17	60302	0	0	0
T18	400260	17	0	0
T24	936	0	0	0
T25	432	0	0	0
T26	70390	0	0	0
T27	531279	5	0	0
T28	68129	0	0	0
T37	394450	8	0	0
T38	398554	10	0	0
T39	253774	2	0	0
T40	17548	7	0	0
T41	0	2	0	0
T42	0	7	0	0
T43	147074	3	0	0
T49	82396	0	0	0
T75	50422	0	0	0
T76	83882	0	0	0
T77	86150	0	0	0
T78	0	3	0	0
T101	167782	0	0	0
T102	54156	0	0	0
T134	0	7	0	0
T135	0	5	0	0
T136	0	7	0	0
T137	0	7	0	0
T138	0	7	0	0
T139	0	7	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T16,T40,T42
1	0	Covered	T16,T40,T42
1	1	Covered	T40,T42,T134

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T40,T42
1	0	Covered	T40,T42,T134
1	1	Covered	T16,T40,T42

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	440076356	163	0	0
SrcPulseCheck_M	148884671	163	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440076356	163	0	0
T16	82564	1	0	0
T17	38650	0	0	0
T18	448701	0	0	0
T24	7324	0	0	0
T25	3731	0	0	0
T26	93589	0	0	0
T27	427872	0	0	0
T28	411122	0	0	0
T37	240117	0	0	0
T40	7849	2	0	0
T42	0	2	0	0
T78	0	2	0	0
T134	0	2	0	0
T135	0	3	0	0
T136	0	2	0	0
T137	0	2	0	0
T138	0	2	0	0
T139	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	163	0	0
T16	16133	1	0	0
T17	60302	0	0	0
T18	400260	0	0	0
T24	936	0	0	0
T25	432	0	0	0
T26	70390	0	0	0
T27	531279	0	0	0
T28	68129	0	0	0
T37	394450	0	0	0
T40	8774	2	0	0
T42	0	2	0	0
T78	0	2	0	0
T134	0	2	0	0
T135	0	3	0	0
T136	0	2	0	0
T137	0	2	0	0
T138	0	2	0	0
T139	0	2	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T40,T41,T42
1	0	Covered	T40,T41,T42
1	1	Covered	T40,T41,T42

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T40,T41,T42
1	0	Covered	T40,T41,T42
1	1	Covered	T40,T41,T42

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	440076356	302	0	0
SrcPulseCheck_M	148884671	302	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440076356	302	0	0
T38	323552	0	0	0
T39	175931	0	0	0
T40	7849	5	0	0
T41	0	2	0	0
T42	0	5	0	0
T43	80538	0	0	0
T62	726	0	0	0
T75	101167	0	0	0
T76	137544	0	0	0
T77	350387	0	0	0
T78	0	1	0	0
T101	179736	0	0	0
T134	0	5	0	0
T135	0	2	0	0
T136	0	5	0	0
T137	0	5	0	0
T138	0	5	0	0
T139	0	5	0	0
T140	1149	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	302	0	0
T38	398554	0	0	0
T39	253774	0	0	0
T40	8774	5	0	0
T41	0	2	0	0
T42	0	5	0	0
T43	147074	0	0	0
T49	82396	0	0	0
T75	50422	0	0	0
T76	83882	0	0	0
T77	86150	0	0	0
T78	0	1	0	0
T101	167782	0	0	0
T102	54156	0	0	0
T134	0	5	0	0
T135	0	2	0	0
T136	0	5	0	0
T137	0	5	0	0
T138	0	5	0	0
T139	0	5	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T3,T4,T6
1	0	Covered	T3,T4,T6
1	1	Covered	T3,T4,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T6
1	0	Covered	T3,T4,T6
1	1	Covered	T3,T4,T6

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	440076356	2226	0	0
SrcPulseCheck_M	148884671	2226	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440076356	2226	0	0
T3	298444	7	0	0
T4	132844	6	0	0
T5	1600	0	0	0
T6	495582	13	0	0
T7	129407	0	0	0
T8	3491	0	0	0
T9	1417	0	0	0
T10	7839	0	0	0
T11	1384	0	0	0
T12	0	10	0	0
T18	0	17	0	0
T23	1199	0	0	0
T27	0	5	0	0
T37	0	8	0	0
T38	0	10	0	0
T39	0	2	0	0
T43	0	3	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	2226	0	0
T3	490671	7	0	0
T4	40260	6	0	0
T6	780398	13	0	0
T7	18282	0	0	0
T8	72	0	0	0
T12	102427	10	0	0
T13	66192	0	0	0
T14	1258	0	0	0
T15	288	0	0	0
T16	16133	0	0	0
T18	0	17	0	0
T27	0	5	0	0
T37	0	8	0	0
T38	0	10	0	0
T39	0	2	0	0
T43	0	3	0	0