Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442449040	2833569	0	0
DepthKnown_A	442449040	442319703	0	0
RvalidKnown_A	442449040	442319703	0	0
WreadyKnown_A	442449040	442319703	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	2833569	0	0
T3	298444	8325	0	0
T4	132844	1665	0	0
T5	1600	0	0	0
T6	495582	14156	0	0
T7	129407	1663	0	0
T8	3491	1665	0	0
T9	1417	0	0	0
T10	7839	0	0	0
T11	1384	0	0	0
T12	0	15802	0	0
T13	0	832	0	0
T16	0	832	0	0
T17	0	832	0	0
T18	0	14144	0	0
T23	1199	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	442319703	0	0
T1	1517	1435	0	0
T2	184929	184860	0	0
T3	298444	298436	0	0
T4	132844	132760	0	0
T5	1600	1527	0	0
T6	495582	495511	0	0
T7	129407	129326	0	0
T8	3491	3410	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	442319703	0	0
T1	1517	1435	0	0
T2	184929	184860	0	0
T3	298444	298436	0	0
T4	132844	132760	0	0
T5	1600	1527	0	0
T6	495582	495511	0	0
T7	129407	129326	0	0
T8	3491	3410	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	442319703	0	0
T1	1517	1435	0	0
T2	184929	184860	0	0
T3	298444	298436	0	0
T4	132844	132760	0	0
T5	1600	1527	0	0
T6	495582	495511	0	0
T7	129407	129326	0	0
T8	3491	3410	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442449040	3163448	0	0
DepthKnown_A	442449040	442319703	0	0
RvalidKnown_A	442449040	442319703	0	0
WreadyKnown_A	442449040	442319703	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	3163448	0	0
T3	298444	10709	0	0
T4	132844	834	0	0
T5	1600	0	0	0
T6	495582	20960	0	0
T7	129407	832	0	0
T8	3491	834	0	0
T9	1417	0	0	0
T10	7839	0	0	0
T11	1384	0	0	0
T12	0	10816	0	0
T13	0	832	0	0
T16	0	832	0	0
T17	0	832	0	0
T18	0	24505	0	0
T23	1199	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	442319703	0	0
T1	1517	1435	0	0
T2	184929	184860	0	0
T3	298444	298436	0	0
T4	132844	132760	0	0
T5	1600	1527	0	0
T6	495582	495511	0	0
T7	129407	129326	0	0
T8	3491	3410	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	442319703	0	0
T1	1517	1435	0	0
T2	184929	184860	0	0
T3	298444	298436	0	0
T4	132844	132760	0	0
T5	1600	1527	0	0
T6	495582	495511	0	0
T7	129407	129326	0	0
T8	3491	3410	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	442319703	0	0
T1	1517	1435	0	0
T2	184929	184860	0	0
T3	298444	298436	0	0
T4	132844	132760	0	0
T5	1600	1527	0	0
T6	495582	495511	0	0
T7	129407	129326	0	0
T8	3491	3410	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442449040	183773	0	0
DepthKnown_A	442449040	442319703	0	0
RvalidKnown_A	442449040	442319703	0	0
WreadyKnown_A	442449040	442319703	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	183773	0	0
T2	184929	1078	0	0
T3	298444	128	0	0
T4	132844	0	0	0
T5	1600	0	0	0
T6	495582	449	0	0
T7	129407	0	0	0
T8	3491	0	0	0
T9	1417	0	0	0
T10	7839	0	0	0
T12	0	845	0	0
T18	0	583	0	0
T23	1199	0	0	0
T26	0	244	0	0
T27	0	439	0	0
T28	0	473	0	0
T37	0	825	0	0
T38	0	290	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	442319703	0	0
T1	1517	1435	0	0
T2	184929	184860	0	0
T3	298444	298436	0	0
T4	132844	132760	0	0
T5	1600	1527	0	0
T6	495582	495511	0	0
T7	129407	129326	0	0
T8	3491	3410	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	442319703	0	0
T1	1517	1435	0	0
T2	184929	184860	0	0
T3	298444	298436	0	0
T4	132844	132760	0	0
T5	1600	1527	0	0
T6	495582	495511	0	0
T7	129407	129326	0	0
T8	3491	3410	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	442319703	0	0
T1	1517	1435	0	0
T2	184929	184860	0	0
T3	298444	298436	0	0
T4	132844	132760	0	0
T5	1600	1527	0	0
T6	495582	495511	0	0
T7	129407	129326	0	0
T8	3491	3410	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442449040	392307	0	0
DepthKnown_A	442449040	442319703	0	0
RvalidKnown_A	442449040	442319703	0	0
WreadyKnown_A	442449040	442319703	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	392307	0	0
T2	184929	3394	0	0
T3	298444	560	0	0
T4	132844	0	0	0
T5	1600	0	0	0
T6	495582	1111	0	0
T7	129407	0	0	0
T8	3491	0	0	0
T9	1417	0	0	0
T10	7839	0	0	0
T12	0	842	0	0
T18	0	2564	0	0
T23	1199	0	0	0
T26	0	244	0	0
T27	0	1933	0	0
T28	0	473	0	0
T37	0	825	0	0
T38	0	1261	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	442319703	0	0
T1	1517	1435	0	0
T2	184929	184860	0	0
T3	298444	298436	0	0
T4	132844	132760	0	0
T5	1600	1527	0	0
T6	495582	495511	0	0
T7	129407	129326	0	0
T8	3491	3410	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	442319703	0	0
T1	1517	1435	0	0
T2	184929	184860	0	0
T3	298444	298436	0	0
T4	132844	132760	0	0
T5	1600	1527	0	0
T6	495582	495511	0	0
T7	129407	129326	0	0
T8	3491	3410	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	442319703	0	0
T1	1517	1435	0	0
T2	184929	184860	0	0
T3	298444	298436	0	0
T4	132844	132760	0	0
T5	1600	1527	0	0
T6	495582	495511	0	0
T7	129407	129326	0	0
T8	3491	3410	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442449040	5763569	0	0
DepthKnown_A	442449040	442319703	0	0
RvalidKnown_A	442449040	442319703	0	0
WreadyKnown_A	442449040	442319703	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	5763569	0	0
T1	1517	49	0	0
T2	184929	7163	0	0
T3	298444	4584	0	0
T4	132844	290	0	0
T5	1600	63	0	0
T6	495582	1442	0	0
T7	129407	5878	0	0
T8	3491	49	0	0
T9	1417	11	0	0
T10	7839	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	442319703	0	0
T1	1517	1435	0	0
T2	184929	184860	0	0
T3	298444	298436	0	0
T4	132844	132760	0	0
T5	1600	1527	0	0
T6	495582	495511	0	0
T7	129407	129326	0	0
T8	3491	3410	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	442319703	0	0
T1	1517	1435	0	0
T2	184929	184860	0	0
T3	298444	298436	0	0
T4	132844	132760	0	0
T5	1600	1527	0	0
T6	495582	495511	0	0
T7	129407	129326	0	0
T8	3491	3410	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	442319703	0	0
T1	1517	1435	0	0
T2	184929	184860	0	0
T3	298444	298436	0	0
T4	132844	132760	0	0
T5	1600	1527	0	0
T6	495582	495511	0	0
T7	129407	129326	0	0
T8	3491	3410	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442449040	11783326	0	0
DepthKnown_A	442449040	442319703	0	0
RvalidKnown_A	442449040	442319703	0	0
WreadyKnown_A	442449040	442319703	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	11783326	0	0
T1	1517	49	0	0
T2	184929	20836	0	0
T3	298444	19502	0	0
T4	132844	850	0	0
T5	1600	63	0	0
T6	495582	5303	0	0
T7	129407	5877	0	0
T8	3491	207	0	0
T9	1417	43	0	0
T10	7839	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	442319703	0	0
T1	1517	1435	0	0
T2	184929	184860	0	0
T3	298444	298436	0	0
T4	132844	132760	0	0
T5	1600	1527	0	0
T6	495582	495511	0	0
T7	129407	129326	0	0
T8	3491	3410	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	442319703	0	0
T1	1517	1435	0	0
T2	184929	184860	0	0
T3	298444	298436	0	0
T4	132844	132760	0	0
T5	1600	1527	0	0
T6	495582	495511	0	0
T7	129407	129326	0	0
T8	3491	3410	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442449040	442319703	0	0
T1	1517	1435	0	0
T2	184929	184860	0	0
T3	298444	298436	0	0
T4	132844	132760	0	0
T5	1600	1527	0	0
T6	495582	495511	0	0
T7	129407	129326	0	0
T8	3491	3410	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0