Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T12,T26
1	0	Covered	T2,T12,T26

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T14
1	0	Unreachable
1	1	Covered	T2,T12,T26

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T6
1	0	Covered	T3,T4,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T3,T4,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	737845698	587542515	0	0
CheckNGreaterZero_A	2862	2862	0	0
GntImpliesReady_A	737845698	3694412	0	0
GntImpliesValid_A	737845698	3694412	0	0
GrantKnown_A	737845698	587542515	0	0
IdxKnown_A	737845698	587542515	0	0
IndexIsCorrect_A	737845698	3694412	0	0
LockArbDecision_A	737845698	0	0	0
NoReadyValidNoGrant_A	737845698	0	0	0
ReadyAndValidImplyGrant_A	737845698	3694412	0	0
ReqAndReadyImplyGrant_A	737845698	3694412	0	0
ReqImpliesValid_A	737845698	3694412	0	0
ReqStaysHighUntilGranted0_M	737845698	0	0	0
RoundRobin_A	737845698	1	0	954
ValidKnown_A	737845698	587542515	0	0
gen_data_port_assertion.DataFlow_A	737845698	3694412	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737845698	587542515	0	0
T1	1517	1435	0	0
T2	1428017	798401	0	0
T3	1279786	787609	0	0
T4	213364	172606	0	0
T5	1600	1527	0	0
T6	2056378	1271754	0	0
T7	165971	147118	0	0
T8	3635	3482	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0
T12	204854	1018422	0	0
T13	132384	66192	0	0
T14	2516	1008	0	0
T15	576	288	0	0
T16	0	15692	0	0
T18	0	121952	0	0
T24	0	936	0	0
T25	0	432	0	0
T26	0	68248	0	0
T27	0	22288	0	0
T28	0	65728	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2862	2862	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737845698	3694412	0	0
T2	806473	9543	0	0
T3	1279786	10123	0	0
T4	213364	856	0	0
T5	1600	0	0	0
T6	2056378	14899	0	0
T7	165971	832	0	0
T8	3635	832	0	0
T9	1417	0	0	0
T10	7839	0	0	0
T12	204854	24048	0	0
T13	132384	832	0	0
T14	2516	0	0	0
T15	576	0	0	0
T16	16133	832	0	0
T18	0	5165	0	0
T23	1199	0	0	0
T26	0	2207	0	0
T27	0	6701	0	0
T28	0	2722	0	0
T34	0	3909	0	0
T37	0	5169	0	0
T38	0	1436	0	0
T39	0	2943	0	0
T43	0	266	0	0
T49	0	3807	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737845698	3694412	0	0
T2	806473	9543	0	0
T3	1279786	10123	0	0
T4	213364	856	0	0
T5	1600	0	0	0
T6	2056378	14899	0	0
T7	165971	832	0	0
T8	3635	832	0	0
T9	1417	0	0	0
T10	7839	0	0	0
T12	204854	24048	0	0
T13	132384	832	0	0
T14	2516	0	0	0
T15	576	0	0	0
T16	16133	832	0	0
T18	0	5165	0	0
T23	1199	0	0	0
T26	0	2207	0	0
T27	0	6701	0	0
T28	0	2722	0	0
T34	0	3909	0	0
T37	0	5169	0	0
T38	0	1436	0	0
T39	0	2943	0	0
T43	0	266	0	0
T49	0	3807	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737845698	587542515	0	0
T1	1517	1435	0	0
T2	1428017	798401	0	0
T3	1279786	787609	0	0
T4	213364	172606	0	0
T5	1600	1527	0	0
T6	2056378	1271754	0	0
T7	165971	147118	0	0
T8	3635	3482	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0
T12	204854	1018422	0	0
T13	132384	66192	0	0
T14	2516	1008	0	0
T15	576	288	0	0
T16	0	15692	0	0
T18	0	121952	0	0
T24	0	936	0	0
T25	0	432	0	0
T26	0	68248	0	0
T27	0	22288	0	0
T28	0	65728	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737845698	587542515	0	0
T1	1517	1435	0	0
T2	1428017	798401	0	0
T3	1279786	787609	0	0
T4	213364	172606	0	0
T5	1600	1527	0	0
T6	2056378	1271754	0	0
T7	165971	147118	0	0
T8	3635	3482	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0
T12	204854	1018422	0	0
T13	132384	66192	0	0
T14	2516	1008	0	0
T15	576	288	0	0
T16	0	15692	0	0
T18	0	121952	0	0
T24	0	936	0	0
T25	0	432	0	0
T26	0	68248	0	0
T27	0	22288	0	0
T28	0	65728	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737845698	3694412	0	0
T2	806473	9543	0	0
T3	1279786	10123	0	0
T4	213364	856	0	0
T5	1600	0	0	0
T6	2056378	14899	0	0
T7	165971	832	0	0
T8	3635	832	0	0
T9	1417	0	0	0
T10	7839	0	0	0
T12	204854	24048	0	0
T13	132384	832	0	0
T14	2516	0	0	0
T15	576	0	0	0
T16	16133	832	0	0
T18	0	5165	0	0
T23	1199	0	0	0
T26	0	2207	0	0
T27	0	6701	0	0
T28	0	2722	0	0
T34	0	3909	0	0
T37	0	5169	0	0
T38	0	1436	0	0
T39	0	2943	0	0
T43	0	266	0	0
T49	0	3807	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737845698	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737845698	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737845698	3694412	0	0
T2	806473	9543	0	0
T3	1279786	10123	0	0
T4	213364	856	0	0
T5	1600	0	0	0
T6	2056378	14899	0	0
T7	165971	832	0	0
T8	3635	832	0	0
T9	1417	0	0	0
T10	7839	0	0	0
T12	204854	24048	0	0
T13	132384	832	0	0
T14	2516	0	0	0
T15	576	0	0	0
T16	16133	832	0	0
T18	0	5165	0	0
T23	1199	0	0	0
T26	0	2207	0	0
T27	0	6701	0	0
T28	0	2722	0	0
T34	0	3909	0	0
T37	0	5169	0	0
T38	0	1436	0	0
T39	0	2943	0	0
T43	0	266	0	0
T49	0	3807	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737845698	3694412	0	0
T2	806473	9543	0	0
T3	1279786	10123	0	0
T4	213364	856	0	0
T5	1600	0	0	0
T6	2056378	14899	0	0
T7	165971	832	0	0
T8	3635	832	0	0
T9	1417	0	0	0
T10	7839	0	0	0
T12	204854	24048	0	0
T13	132384	832	0	0
T14	2516	0	0	0
T15	576	0	0	0
T16	16133	832	0	0
T18	0	5165	0	0
T23	1199	0	0	0
T26	0	2207	0	0
T27	0	6701	0	0
T28	0	2722	0	0
T34	0	3909	0	0
T37	0	5169	0	0
T38	0	1436	0	0
T39	0	2943	0	0
T43	0	266	0	0
T49	0	3807	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737845698	3694412	0	0
T2	806473	9543	0	0
T3	1279786	10123	0	0
T4	213364	856	0	0
T5	1600	0	0	0
T6	2056378	14899	0	0
T7	165971	832	0	0
T8	3635	832	0	0
T9	1417	0	0	0
T10	7839	0	0	0
T12	204854	24048	0	0
T13	132384	832	0	0
T14	2516	0	0	0
T15	576	0	0	0
T16	16133	832	0	0
T18	0	5165	0	0
T23	1199	0	0	0
T26	0	2207	0	0
T27	0	6701	0	0
T28	0	2722	0	0
T34	0	3909	0	0
T37	0	5169	0	0
T38	0	1436	0	0
T39	0	2943	0	0
T43	0	266	0	0
T49	0	3807	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	737845698	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737845698	1	0	954
T50	225706	1	0	1
T51	2657	0	0	1
T52	507348	0	0	1
T53	439336	0	0	1
T54	28617	0	0	1
T55	4458	0	0	1
T56	36601	0	0	1
T57	140057	0	0	1
T58	19149	0	0	1
T59	247126	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737845698	587542515	0	0
T1	1517	1435	0	0
T2	1428017	798401	0	0
T3	1279786	787609	0	0
T4	213364	172606	0	0
T5	1600	1527	0	0
T6	2056378	1271754	0	0
T7	165971	147118	0	0
T8	3635	3482	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0
T12	204854	1018422	0	0
T13	132384	66192	0	0
T14	2516	1008	0	0
T15	576	288	0	0
T16	0	15692	0	0
T18	0	121952	0	0
T24	0	936	0	0
T25	0	432	0	0
T26	0	68248	0	0
T27	0	22288	0	0
T28	0	65728	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737845698	3694412	0	0
T2	806473	9543	0	0
T3	1279786	10123	0	0
T4	213364	856	0	0
T5	1600	0	0	0
T6	2056378	14899	0	0
T7	165971	832	0	0
T8	3635	832	0	0
T9	1417	0	0	0
T10	7839	0	0	0
T12	204854	24048	0	0
T13	132384	832	0	0
T14	2516	0	0	0
T15	576	0	0	0
T16	16133	832	0	0
T18	0	5165	0	0
T23	1199	0	0	0
T26	0	2207	0	0
T27	0	6701	0	0
T28	0	2722	0	0
T34	0	3909	0	0
T37	0	5169	0	0
T38	0	1436	0	0
T39	0	2943	0	0
T43	0	266	0	0
T49	0	3807	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T12,T26
1	0	Covered	T2,T12,T26

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T14
1	0	Unreachable
1	1	Covered	T2,T12,T26

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T12,T26
0	0	1	Unreachable
0	0	0	Covered	T2,T12,T14

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T12,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T12,T26
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	148884671	26737931	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	148884671	617712	0	0
GntImpliesValid_A	148884671	617712	0	0
GrantKnown_A	148884671	26737931	0	0
IdxKnown_A	148884671	26737931	0	0
IndexIsCorrect_A	148884671	617712	0	0
LockArbDecision_A	148884671	0	0	0
NoReadyValidNoGrant_A	148884671	0	0	0
ReadyAndValidImplyGrant_A	148884671	617712	0	0
ReqAndReadyImplyGrant_A	148884671	617712	0	0
ReqImpliesValid_A	148884671	617712	0	0
ReqStaysHighUntilGranted0_M	148884671	0	0	0
RoundRobin_A	148884671	0	0	0
ValidKnown_A	148884671	26737931	0	0
gen_data_port_assertion.DataFlow_A	148884671	617712	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	26737931	0	0
T2	621544	613536	0	0
T3	490671	0	0	0
T4	40260	0	0	0
T6	780398	0	0	0
T7	18282	0	0	0
T8	72	0	0	0
T12	102427	100600	0	0
T13	66192	0	0	0
T14	1258	1008	0	0
T15	288	288	0	0
T18	0	121952	0	0
T24	0	936	0	0
T25	0	432	0	0
T26	0	68248	0	0
T27	0	22288	0	0
T28	0	65728	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	617712	0	0
T2	621544	6391	0	0
T3	490671	0	0	0
T4	40260	0	0	0
T6	780398	0	0	0
T7	18282	0	0	0
T8	72	0	0	0
T12	102427	2494	0	0
T13	66192	0	0	0
T14	1258	0	0	0
T15	288	0	0	0
T18	0	2767	0	0
T26	0	1480	0	0
T27	0	1029	0	0
T28	0	2722	0	0
T34	0	3909	0	0
T37	0	4642	0	0
T39	0	2935	0	0
T49	0	3807	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	617712	0	0
T2	621544	6391	0	0
T3	490671	0	0	0
T4	40260	0	0	0
T6	780398	0	0	0
T7	18282	0	0	0
T8	72	0	0	0
T12	102427	2494	0	0
T13	66192	0	0	0
T14	1258	0	0	0
T15	288	0	0	0
T18	0	2767	0	0
T26	0	1480	0	0
T27	0	1029	0	0
T28	0	2722	0	0
T34	0	3909	0	0
T37	0	4642	0	0
T39	0	2935	0	0
T49	0	3807	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	26737931	0	0
T2	621544	613536	0	0
T3	490671	0	0	0
T4	40260	0	0	0
T6	780398	0	0	0
T7	18282	0	0	0
T8	72	0	0	0
T12	102427	100600	0	0
T13	66192	0	0	0
T14	1258	1008	0	0
T15	288	288	0	0
T18	0	121952	0	0
T24	0	936	0	0
T25	0	432	0	0
T26	0	68248	0	0
T27	0	22288	0	0
T28	0	65728	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	26737931	0	0
T2	621544	613536	0	0
T3	490671	0	0	0
T4	40260	0	0	0
T6	780398	0	0	0
T7	18282	0	0	0
T8	72	0	0	0
T12	102427	100600	0	0
T13	66192	0	0	0
T14	1258	1008	0	0
T15	288	288	0	0
T18	0	121952	0	0
T24	0	936	0	0
T25	0	432	0	0
T26	0	68248	0	0
T27	0	22288	0	0
T28	0	65728	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	617712	0	0
T2	621544	6391	0	0
T3	490671	0	0	0
T4	40260	0	0	0
T6	780398	0	0	0
T7	18282	0	0	0
T8	72	0	0	0
T12	102427	2494	0	0
T13	66192	0	0	0
T14	1258	0	0	0
T15	288	0	0	0
T18	0	2767	0	0
T26	0	1480	0	0
T27	0	1029	0	0
T28	0	2722	0	0
T34	0	3909	0	0
T37	0	4642	0	0
T39	0	2935	0	0
T49	0	3807	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	617712	0	0
T2	621544	6391	0	0
T3	490671	0	0	0
T4	40260	0	0	0
T6	780398	0	0	0
T7	18282	0	0	0
T8	72	0	0	0
T12	102427	2494	0	0
T13	66192	0	0	0
T14	1258	0	0	0
T15	288	0	0	0
T18	0	2767	0	0
T26	0	1480	0	0
T27	0	1029	0	0
T28	0	2722	0	0
T34	0	3909	0	0
T37	0	4642	0	0
T39	0	2935	0	0
T49	0	3807	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	617712	0	0
T2	621544	6391	0	0
T3	490671	0	0	0
T4	40260	0	0	0
T6	780398	0	0	0
T7	18282	0	0	0
T8	72	0	0	0
T12	102427	2494	0	0
T13	66192	0	0	0
T14	1258	0	0	0
T15	288	0	0	0
T18	0	2767	0	0
T26	0	1480	0	0
T27	0	1029	0	0
T28	0	2722	0	0
T34	0	3909	0	0
T37	0	4642	0	0
T39	0	2935	0	0
T49	0	3807	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	617712	0	0
T2	621544	6391	0	0
T3	490671	0	0	0
T4	40260	0	0	0
T6	780398	0	0	0
T7	18282	0	0	0
T8	72	0	0	0
T12	102427	2494	0	0
T13	66192	0	0	0
T14	1258	0	0	0
T15	288	0	0	0
T18	0	2767	0	0
T26	0	1480	0	0
T27	0	1029	0	0
T28	0	2722	0	0
T34	0	3909	0	0
T37	0	4642	0	0
T39	0	2935	0	0
T49	0	3807	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	26737931	0	0
T2	621544	613536	0	0
T3	490671	0	0	0
T4	40260	0	0	0
T6	780398	0	0	0
T7	18282	0	0	0
T8	72	0	0	0
T12	102427	100600	0	0
T13	66192	0	0	0
T14	1258	1008	0	0
T15	288	288	0	0
T18	0	121952	0	0
T24	0	936	0	0
T25	0	432	0	0
T26	0	68248	0	0
T27	0	22288	0	0
T28	0	65728	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	617712	0	0
T2	621544	6391	0	0
T3	490671	0	0	0
T4	40260	0	0	0
T6	780398	0	0	0
T7	18282	0	0	0
T8	72	0	0	0
T12	102427	2494	0	0
T13	66192	0	0	0
T14	1258	0	0	0
T15	288	0	0	0
T18	0	2767	0	0
T26	0	1480	0	0
T27	0	1029	0	0
T28	0	2722	0	0
T34	0	3909	0	0
T37	0	4642	0	0
T39	0	2935	0	0
T49	0	3807	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T6
1	0	Covered	T3,T4,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T3,T4,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T6
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	148884671	120814424	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	148884671	818550	0	0
GntImpliesValid_A	148884671	818550	0	0
GrantKnown_A	148884671	120814424	0	0
IdxKnown_A	148884671	120814424	0	0
IndexIsCorrect_A	148884671	818550	0	0
LockArbDecision_A	148884671	0	0	0
NoReadyValidNoGrant_A	148884671	0	0	0
ReadyAndValidImplyGrant_A	148884671	818550	0	0
ReqAndReadyImplyGrant_A	148884671	818550	0	0
ReqImpliesValid_A	148884671	818550	0	0
ReqStaysHighUntilGranted0_M	148884671	0	0	0
RoundRobin_A	148884671	0	0	0
ValidKnown_A	148884671	120814424	0	0
gen_data_port_assertion.DataFlow_A	148884671	818550	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	120814424	0	0
T2	621544	5	0	0
T3	490671	489173	0	0
T4	40260	39846	0	0
T6	780398	776243	0	0
T7	18282	17792	0	0
T8	72	72	0	0
T12	102427	917822	0	0
T13	66192	66192	0	0
T14	1258	0	0	0
T15	288	0	0	0
T16	0	15692	0	0
T17	0	59722	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	818550	0	0
T3	490671	4990	0	0
T4	40260	12	0	0
T6	780398	5273	0	0
T7	18282	0	0	0
T8	72	0	0	0
T12	102427	9200	0	0
T13	66192	0	0	0
T14	1258	0	0	0
T15	288	0	0	0
T16	16133	0	0	0
T18	0	2398	0	0
T27	0	5672	0	0
T37	0	527	0	0
T38	0	1436	0	0
T39	0	8	0	0
T43	0	266	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	818550	0	0
T3	490671	4990	0	0
T4	40260	12	0	0
T6	780398	5273	0	0
T7	18282	0	0	0
T8	72	0	0	0
T12	102427	9200	0	0
T13	66192	0	0	0
T14	1258	0	0	0
T15	288	0	0	0
T16	16133	0	0	0
T18	0	2398	0	0
T27	0	5672	0	0
T37	0	527	0	0
T38	0	1436	0	0
T39	0	8	0	0
T43	0	266	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	120814424	0	0
T2	621544	5	0	0
T3	490671	489173	0	0
T4	40260	39846	0	0
T6	780398	776243	0	0
T7	18282	17792	0	0
T8	72	72	0	0
T12	102427	917822	0	0
T13	66192	66192	0	0
T14	1258	0	0	0
T15	288	0	0	0
T16	0	15692	0	0
T17	0	59722	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	120814424	0	0
T2	621544	5	0	0
T3	490671	489173	0	0
T4	40260	39846	0	0
T6	780398	776243	0	0
T7	18282	17792	0	0
T8	72	72	0	0
T12	102427	917822	0	0
T13	66192	66192	0	0
T14	1258	0	0	0
T15	288	0	0	0
T16	0	15692	0	0
T17	0	59722	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	818550	0	0
T3	490671	4990	0	0
T4	40260	12	0	0
T6	780398	5273	0	0
T7	18282	0	0	0
T8	72	0	0	0
T12	102427	9200	0	0
T13	66192	0	0	0
T14	1258	0	0	0
T15	288	0	0	0
T16	16133	0	0	0
T18	0	2398	0	0
T27	0	5672	0	0
T37	0	527	0	0
T38	0	1436	0	0
T39	0	8	0	0
T43	0	266	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	818550	0	0
T3	490671	4990	0	0
T4	40260	12	0	0
T6	780398	5273	0	0
T7	18282	0	0	0
T8	72	0	0	0
T12	102427	9200	0	0
T13	66192	0	0	0
T14	1258	0	0	0
T15	288	0	0	0
T16	16133	0	0	0
T18	0	2398	0	0
T27	0	5672	0	0
T37	0	527	0	0
T38	0	1436	0	0
T39	0	8	0	0
T43	0	266	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	818550	0	0
T3	490671	4990	0	0
T4	40260	12	0	0
T6	780398	5273	0	0
T7	18282	0	0	0
T8	72	0	0	0
T12	102427	9200	0	0
T13	66192	0	0	0
T14	1258	0	0	0
T15	288	0	0	0
T16	16133	0	0	0
T18	0	2398	0	0
T27	0	5672	0	0
T37	0	527	0	0
T38	0	1436	0	0
T39	0	8	0	0
T43	0	266	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	818550	0	0
T3	490671	4990	0	0
T4	40260	12	0	0
T6	780398	5273	0	0
T7	18282	0	0	0
T8	72	0	0	0
T12	102427	9200	0	0
T13	66192	0	0	0
T14	1258	0	0	0
T15	288	0	0	0
T16	16133	0	0	0
T18	0	2398	0	0
T27	0	5672	0	0
T37	0	527	0	0
T38	0	1436	0	0
T39	0	8	0	0
T43	0	266	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	120814424	0	0
T2	621544	5	0	0
T3	490671	489173	0	0
T4	40260	39846	0	0
T6	780398	776243	0	0
T7	18282	17792	0	0
T8	72	72	0	0
T12	102427	917822	0	0
T13	66192	66192	0	0
T14	1258	0	0	0
T15	288	0	0	0
T16	0	15692	0	0
T17	0	59722	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148884671	818550	0	0
T3	490671	4990	0	0
T4	40260	12	0	0
T6	780398	5273	0	0
T7	18282	0	0	0
T8	72	0	0	0
T12	102427	9200	0	0
T13	66192	0	0	0
T14	1258	0	0	0
T15	288	0	0	0
T16	16133	0	0	0
T18	0	2398	0	0
T27	0	5672	0	0
T37	0	527	0	0
T38	0	1436	0	0
T39	0	8	0	0
T43	0	266	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	440076356	439990160	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	440076356	2258150	0	0
GntImpliesValid_A	440076356	2258150	0	0
GrantKnown_A	440076356	439990160	0	0
IdxKnown_A	440076356	439990160	0	0
IndexIsCorrect_A	440076356	2258150	0	0
LockArbDecision_A	440076356	0	0	0
NoReadyValidNoGrant_A	440076356	0	0	0
ReadyAndValidImplyGrant_A	440076356	2258150	0	0
ReqAndReadyImplyGrant_A	440076356	2258150	0	0
ReqImpliesValid_A	440076356	2258150	0	0
ReqStaysHighUntilGranted0_M	440076356	0	0	0
RoundRobin_A	440076356	1	0	954
ValidKnown_A	440076356	439990160	0	0
gen_data_port_assertion.DataFlow_A	440076356	2258150	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440076356	439990160	0	0
T1	1517	1435	0	0
T2	184929	184860	0	0
T3	298444	298436	0	0
T4	132844	132760	0	0
T5	1600	1527	0	0
T6	495582	495511	0	0
T7	129407	129326	0	0
T8	3491	3410	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440076356	2258150	0	0
T2	184929	3152	0	0
T3	298444	5133	0	0
T4	132844	844	0	0
T5	1600	0	0	0
T6	495582	9626	0	0
T7	129407	832	0	0
T8	3491	832	0	0
T9	1417	0	0	0
T10	7839	0	0	0
T12	0	12354	0	0
T13	0	832	0	0
T16	0	832	0	0
T23	1199	0	0	0
T26	0	727	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440076356	2258150	0	0
T2	184929	3152	0	0
T3	298444	5133	0	0
T4	132844	844	0	0
T5	1600	0	0	0
T6	495582	9626	0	0
T7	129407	832	0	0
T8	3491	832	0	0
T9	1417	0	0	0
T10	7839	0	0	0
T12	0	12354	0	0
T13	0	832	0	0
T16	0	832	0	0
T23	1199	0	0	0
T26	0	727	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440076356	439990160	0	0
T1	1517	1435	0	0
T2	184929	184860	0	0
T3	298444	298436	0	0
T4	132844	132760	0	0
T5	1600	1527	0	0
T6	495582	495511	0	0
T7	129407	129326	0	0
T8	3491	3410	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440076356	439990160	0	0
T1	1517	1435	0	0
T2	184929	184860	0	0
T3	298444	298436	0	0
T4	132844	132760	0	0
T5	1600	1527	0	0
T6	495582	495511	0	0
T7	129407	129326	0	0
T8	3491	3410	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440076356	2258150	0	0
T2	184929	3152	0	0
T3	298444	5133	0	0
T4	132844	844	0	0
T5	1600	0	0	0
T6	495582	9626	0	0
T7	129407	832	0	0
T8	3491	832	0	0
T9	1417	0	0	0
T10	7839	0	0	0
T12	0	12354	0	0
T13	0	832	0	0
T16	0	832	0	0
T23	1199	0	0	0
T26	0	727	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440076356	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440076356	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440076356	2258150	0	0
T2	184929	3152	0	0
T3	298444	5133	0	0
T4	132844	844	0	0
T5	1600	0	0	0
T6	495582	9626	0	0
T7	129407	832	0	0
T8	3491	832	0	0
T9	1417	0	0	0
T10	7839	0	0	0
T12	0	12354	0	0
T13	0	832	0	0
T16	0	832	0	0
T23	1199	0	0	0
T26	0	727	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440076356	2258150	0	0
T2	184929	3152	0	0
T3	298444	5133	0	0
T4	132844	844	0	0
T5	1600	0	0	0
T6	495582	9626	0	0
T7	129407	832	0	0
T8	3491	832	0	0
T9	1417	0	0	0
T10	7839	0	0	0
T12	0	12354	0	0
T13	0	832	0	0
T16	0	832	0	0
T23	1199	0	0	0
T26	0	727	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440076356	2258150	0	0
T2	184929	3152	0	0
T3	298444	5133	0	0
T4	132844	844	0	0
T5	1600	0	0	0
T6	495582	9626	0	0
T7	129407	832	0	0
T8	3491	832	0	0
T9	1417	0	0	0
T10	7839	0	0	0
T12	0	12354	0	0
T13	0	832	0	0
T16	0	832	0	0
T23	1199	0	0	0
T26	0	727	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	440076356	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440076356	1	0	954
T50	225706	1	0	1
T51	2657	0	0	1
T52	507348	0	0	1
T53	439336	0	0	1
T54	28617	0	0	1
T55	4458	0	0	1
T56	36601	0	0	1
T57	140057	0	0	1
T58	19149	0	0	1
T59	247126	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440076356	439990160	0	0
T1	1517	1435	0	0
T2	184929	184860	0	0
T3	298444	298436	0	0
T4	132844	132760	0	0
T5	1600	1527	0	0
T6	495582	495511	0	0
T7	129407	129326	0	0
T8	3491	3410	0	0
T9	1417	1356	0	0
T10	7839	5539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440076356	2258150	0	0
T2	184929	3152	0	0
T3	298444	5133	0	0
T4	132844	844	0	0
T5	1600	0	0	0
T6	495582	9626	0	0
T7	129407	832	0	0
T8	3491	832	0	0
T9	1417	0	0	0
T10	7839	0	0	0
T12	0	12354	0	0
T13	0	832	0	0
T16	0	832	0	0
T23	1199	0	0	0
T26	0	727	0	0