Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
3077 |
0 |
0 |
T63 |
14007 |
6 |
0 |
0 |
T64 |
6942 |
96 |
0 |
0 |
T65 |
7300 |
96 |
0 |
0 |
T84 |
71834 |
1 |
0 |
0 |
T85 |
20181 |
187 |
0 |
0 |
T86 |
108962 |
6 |
0 |
0 |
T94 |
14837 |
4 |
0 |
0 |
T97 |
5259 |
9 |
0 |
0 |
T98 |
11623 |
5 |
0 |
0 |
T100 |
1879 |
1 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
2013 |
0 |
0 |
T63 |
14007 |
9 |
0 |
0 |
T84 |
71834 |
75 |
0 |
0 |
T86 |
108962 |
100 |
0 |
0 |
T87 |
32550 |
20 |
0 |
0 |
T94 |
14837 |
6 |
0 |
0 |
T104 |
77190 |
473 |
0 |
0 |
T133 |
20567 |
48 |
0 |
0 |
T141 |
10280 |
15 |
0 |
0 |
T142 |
108145 |
120 |
0 |
0 |
T143 |
13389 |
96 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
1990 |
0 |
0 |
T63 |
14007 |
17 |
0 |
0 |
T84 |
71834 |
97 |
0 |
0 |
T86 |
108962 |
125 |
0 |
0 |
T87 |
32550 |
6 |
0 |
0 |
T94 |
14837 |
17 |
0 |
0 |
T104 |
77190 |
489 |
0 |
0 |
T133 |
20567 |
52 |
0 |
0 |
T141 |
10280 |
17 |
0 |
0 |
T142 |
108145 |
121 |
0 |
0 |
T144 |
5262 |
13 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
2619 |
0 |
0 |
T63 |
14007 |
6 |
0 |
0 |
T84 |
71834 |
182 |
0 |
0 |
T86 |
108962 |
253 |
0 |
0 |
T87 |
32550 |
29 |
0 |
0 |
T94 |
14837 |
24 |
0 |
0 |
T104 |
77190 |
513 |
0 |
0 |
T133 |
20567 |
76 |
0 |
0 |
T141 |
10280 |
23 |
0 |
0 |
T142 |
108145 |
232 |
0 |
0 |
T144 |
5262 |
7 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
13395 |
0 |
0 |
T63 |
14007 |
18 |
0 |
0 |
T84 |
71834 |
1236 |
0 |
0 |
T86 |
108962 |
2018 |
0 |
0 |
T87 |
32550 |
487 |
0 |
0 |
T94 |
14837 |
76 |
0 |
0 |
T104 |
77190 |
506 |
0 |
0 |
T133 |
20567 |
100 |
0 |
0 |
T141 |
10280 |
127 |
0 |
0 |
T142 |
108145 |
2808 |
0 |
0 |
T144 |
5262 |
75 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
12312 |
0 |
0 |
T63 |
14007 |
133 |
0 |
0 |
T84 |
71834 |
1336 |
0 |
0 |
T86 |
108962 |
1315 |
0 |
0 |
T87 |
32550 |
342 |
0 |
0 |
T94 |
14837 |
219 |
0 |
0 |
T104 |
77190 |
499 |
0 |
0 |
T133 |
20567 |
66 |
0 |
0 |
T141 |
10280 |
131 |
0 |
0 |
T142 |
108145 |
1666 |
0 |
0 |
T144 |
5262 |
3 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
13983 |
0 |
0 |
T63 |
14007 |
149 |
0 |
0 |
T84 |
71834 |
1731 |
0 |
0 |
T86 |
108962 |
2434 |
0 |
0 |
T87 |
32550 |
356 |
0 |
0 |
T94 |
14837 |
133 |
0 |
0 |
T104 |
77190 |
480 |
0 |
0 |
T133 |
20567 |
90 |
0 |
0 |
T141 |
10280 |
20 |
0 |
0 |
T142 |
108145 |
1762 |
0 |
0 |
T144 |
5262 |
6 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
12121 |
0 |
0 |
T63 |
14007 |
91 |
0 |
0 |
T84 |
71834 |
1483 |
0 |
0 |
T86 |
108962 |
1752 |
0 |
0 |
T87 |
32550 |
282 |
0 |
0 |
T94 |
14837 |
89 |
0 |
0 |
T104 |
77190 |
465 |
0 |
0 |
T133 |
20567 |
100 |
0 |
0 |
T141 |
10280 |
234 |
0 |
0 |
T142 |
108145 |
1418 |
0 |
0 |
T144 |
5262 |
48 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
12999 |
0 |
0 |
T63 |
14007 |
112 |
0 |
0 |
T84 |
71834 |
884 |
0 |
0 |
T86 |
108962 |
2095 |
0 |
0 |
T87 |
32550 |
344 |
0 |
0 |
T94 |
14837 |
132 |
0 |
0 |
T104 |
77190 |
483 |
0 |
0 |
T133 |
20567 |
69 |
0 |
0 |
T141 |
10280 |
109 |
0 |
0 |
T142 |
108145 |
2308 |
0 |
0 |
T144 |
5262 |
13 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
13548 |
0 |
0 |
T63 |
14007 |
133 |
0 |
0 |
T84 |
71834 |
926 |
0 |
0 |
T86 |
108962 |
2373 |
0 |
0 |
T87 |
32550 |
303 |
0 |
0 |
T94 |
14837 |
194 |
0 |
0 |
T104 |
77190 |
525 |
0 |
0 |
T133 |
20567 |
85 |
0 |
0 |
T141 |
10280 |
134 |
0 |
0 |
T142 |
108145 |
1844 |
0 |
0 |
T144 |
5262 |
65 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
13255 |
0 |
0 |
T63 |
14007 |
61 |
0 |
0 |
T84 |
71834 |
1502 |
0 |
0 |
T86 |
108962 |
2031 |
0 |
0 |
T87 |
32550 |
429 |
0 |
0 |
T94 |
14837 |
93 |
0 |
0 |
T104 |
77190 |
487 |
0 |
0 |
T133 |
20567 |
80 |
0 |
0 |
T141 |
10280 |
127 |
0 |
0 |
T142 |
108145 |
2641 |
0 |
0 |
T144 |
5262 |
70 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
12113 |
0 |
0 |
T63 |
14007 |
158 |
0 |
0 |
T84 |
71834 |
1260 |
0 |
0 |
T86 |
108962 |
2151 |
0 |
0 |
T87 |
32550 |
379 |
0 |
0 |
T94 |
14837 |
79 |
0 |
0 |
T104 |
77190 |
527 |
0 |
0 |
T133 |
20567 |
40 |
0 |
0 |
T141 |
10280 |
14 |
0 |
0 |
T142 |
108145 |
2002 |
0 |
0 |
T144 |
5262 |
5 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
5777 |
0 |
0 |
T63 |
14007 |
84 |
0 |
0 |
T84 |
71834 |
515 |
0 |
0 |
T86 |
108962 |
585 |
0 |
0 |
T87 |
32550 |
143 |
0 |
0 |
T94 |
14837 |
73 |
0 |
0 |
T104 |
77190 |
484 |
0 |
0 |
T133 |
20567 |
51 |
0 |
0 |
T141 |
10280 |
77 |
0 |
0 |
T142 |
108145 |
749 |
0 |
0 |
T144 |
5262 |
1 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
6260 |
0 |
0 |
T63 |
14007 |
48 |
0 |
0 |
T84 |
71834 |
609 |
0 |
0 |
T86 |
108962 |
838 |
0 |
0 |
T87 |
32550 |
158 |
0 |
0 |
T94 |
14837 |
20 |
0 |
0 |
T104 |
77190 |
485 |
0 |
0 |
T133 |
20567 |
37 |
0 |
0 |
T141 |
10280 |
127 |
0 |
0 |
T142 |
108145 |
1061 |
0 |
0 |
T144 |
5262 |
6 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
5912 |
0 |
0 |
T63 |
14007 |
77 |
0 |
0 |
T84 |
71834 |
497 |
0 |
0 |
T86 |
108962 |
817 |
0 |
0 |
T87 |
32550 |
140 |
0 |
0 |
T94 |
14837 |
95 |
0 |
0 |
T104 |
77190 |
491 |
0 |
0 |
T133 |
20567 |
40 |
0 |
0 |
T141 |
10280 |
131 |
0 |
0 |
T142 |
108145 |
757 |
0 |
0 |
T144 |
5262 |
6 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
5918 |
0 |
0 |
T63 |
14007 |
14 |
0 |
0 |
T84 |
71834 |
494 |
0 |
0 |
T86 |
108962 |
674 |
0 |
0 |
T87 |
32550 |
123 |
0 |
0 |
T94 |
14837 |
10 |
0 |
0 |
T104 |
77190 |
503 |
0 |
0 |
T133 |
20567 |
68 |
0 |
0 |
T141 |
10280 |
79 |
0 |
0 |
T142 |
108145 |
889 |
0 |
0 |
T144 |
5262 |
36 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
6131 |
0 |
0 |
T63 |
14007 |
84 |
0 |
0 |
T84 |
71834 |
584 |
0 |
0 |
T86 |
108962 |
957 |
0 |
0 |
T87 |
32550 |
112 |
0 |
0 |
T94 |
14837 |
26 |
0 |
0 |
T104 |
77190 |
477 |
0 |
0 |
T133 |
20567 |
48 |
0 |
0 |
T141 |
10280 |
91 |
0 |
0 |
T142 |
108145 |
681 |
0 |
0 |
T144 |
5262 |
5 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
6852 |
0 |
0 |
T63 |
14007 |
66 |
0 |
0 |
T84 |
71834 |
503 |
0 |
0 |
T86 |
108962 |
634 |
0 |
0 |
T87 |
32550 |
179 |
0 |
0 |
T94 |
14837 |
80 |
0 |
0 |
T104 |
77190 |
516 |
0 |
0 |
T133 |
20567 |
21 |
0 |
0 |
T141 |
10280 |
9 |
0 |
0 |
T142 |
108145 |
1031 |
0 |
0 |
T144 |
5262 |
33 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
5864 |
0 |
0 |
T63 |
14007 |
75 |
0 |
0 |
T84 |
71834 |
529 |
0 |
0 |
T86 |
108962 |
935 |
0 |
0 |
T87 |
32550 |
138 |
0 |
0 |
T94 |
14837 |
38 |
0 |
0 |
T104 |
77190 |
535 |
0 |
0 |
T133 |
20567 |
19 |
0 |
0 |
T141 |
10280 |
62 |
0 |
0 |
T142 |
108145 |
623 |
0 |
0 |
T143 |
13389 |
43 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
5852 |
0 |
0 |
T63 |
14007 |
54 |
0 |
0 |
T84 |
71834 |
378 |
0 |
0 |
T86 |
108962 |
872 |
0 |
0 |
T87 |
32550 |
77 |
0 |
0 |
T94 |
14837 |
117 |
0 |
0 |
T104 |
77190 |
470 |
0 |
0 |
T133 |
20567 |
69 |
0 |
0 |
T141 |
10280 |
64 |
0 |
0 |
T142 |
108145 |
796 |
0 |
0 |
T144 |
5262 |
31 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
6247 |
0 |
0 |
T63 |
14007 |
65 |
0 |
0 |
T84 |
71834 |
385 |
0 |
0 |
T86 |
108962 |
718 |
0 |
0 |
T87 |
32550 |
91 |
0 |
0 |
T94 |
14837 |
10 |
0 |
0 |
T104 |
77190 |
475 |
0 |
0 |
T133 |
20567 |
66 |
0 |
0 |
T141 |
10280 |
57 |
0 |
0 |
T142 |
108145 |
1044 |
0 |
0 |
T144 |
5262 |
31 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
5702 |
0 |
0 |
T63 |
14007 |
22 |
0 |
0 |
T84 |
71834 |
568 |
0 |
0 |
T86 |
108962 |
729 |
0 |
0 |
T87 |
32550 |
135 |
0 |
0 |
T94 |
14837 |
44 |
0 |
0 |
T104 |
77190 |
480 |
0 |
0 |
T133 |
20567 |
65 |
0 |
0 |
T141 |
10280 |
53 |
0 |
0 |
T142 |
108145 |
662 |
0 |
0 |
T144 |
5262 |
11 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
5368 |
0 |
0 |
T63 |
14007 |
15 |
0 |
0 |
T84 |
71834 |
409 |
0 |
0 |
T86 |
108962 |
937 |
0 |
0 |
T87 |
32550 |
143 |
0 |
0 |
T94 |
14837 |
66 |
0 |
0 |
T104 |
77190 |
505 |
0 |
0 |
T133 |
20567 |
42 |
0 |
0 |
T141 |
10280 |
64 |
0 |
0 |
T142 |
108145 |
736 |
0 |
0 |
T144 |
5262 |
35 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
5382 |
0 |
0 |
T63 |
14007 |
19 |
0 |
0 |
T84 |
71834 |
344 |
0 |
0 |
T86 |
108962 |
904 |
0 |
0 |
T87 |
32550 |
176 |
0 |
0 |
T94 |
14837 |
25 |
0 |
0 |
T104 |
77190 |
428 |
0 |
0 |
T133 |
20567 |
70 |
0 |
0 |
T141 |
10280 |
7 |
0 |
0 |
T142 |
108145 |
628 |
0 |
0 |
T144 |
5262 |
5 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
5897 |
0 |
0 |
T63 |
14007 |
67 |
0 |
0 |
T84 |
71834 |
460 |
0 |
0 |
T86 |
108962 |
708 |
0 |
0 |
T87 |
32550 |
154 |
0 |
0 |
T94 |
14837 |
100 |
0 |
0 |
T104 |
77190 |
468 |
0 |
0 |
T133 |
20567 |
55 |
0 |
0 |
T141 |
10280 |
23 |
0 |
0 |
T142 |
108145 |
789 |
0 |
0 |
T144 |
5262 |
36 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
6469 |
0 |
0 |
T63 |
14007 |
68 |
0 |
0 |
T84 |
71834 |
576 |
0 |
0 |
T86 |
108962 |
810 |
0 |
0 |
T87 |
32550 |
118 |
0 |
0 |
T94 |
14837 |
86 |
0 |
0 |
T104 |
77190 |
491 |
0 |
0 |
T133 |
20567 |
83 |
0 |
0 |
T141 |
10280 |
17 |
0 |
0 |
T142 |
108145 |
962 |
0 |
0 |
T144 |
5262 |
21 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
5764 |
0 |
0 |
T63 |
14007 |
54 |
0 |
0 |
T84 |
71834 |
384 |
0 |
0 |
T86 |
108962 |
703 |
0 |
0 |
T87 |
32550 |
110 |
0 |
0 |
T94 |
14837 |
60 |
0 |
0 |
T104 |
77190 |
472 |
0 |
0 |
T133 |
20567 |
37 |
0 |
0 |
T141 |
10280 |
60 |
0 |
0 |
T142 |
108145 |
988 |
0 |
0 |
T144 |
5262 |
26 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
6052 |
0 |
0 |
T63 |
14007 |
68 |
0 |
0 |
T84 |
71834 |
548 |
0 |
0 |
T86 |
108962 |
889 |
0 |
0 |
T87 |
32550 |
196 |
0 |
0 |
T94 |
14837 |
66 |
0 |
0 |
T104 |
77190 |
509 |
0 |
0 |
T133 |
20567 |
21 |
0 |
0 |
T141 |
10280 |
110 |
0 |
0 |
T142 |
108145 |
651 |
0 |
0 |
T144 |
5262 |
35 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
5461 |
0 |
0 |
T63 |
14007 |
3 |
0 |
0 |
T84 |
71834 |
492 |
0 |
0 |
T86 |
108962 |
687 |
0 |
0 |
T87 |
32550 |
121 |
0 |
0 |
T94 |
14837 |
39 |
0 |
0 |
T104 |
77190 |
522 |
0 |
0 |
T133 |
20567 |
59 |
0 |
0 |
T141 |
10280 |
59 |
0 |
0 |
T142 |
108145 |
710 |
0 |
0 |
T143 |
13389 |
17 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
5997 |
0 |
0 |
T63 |
14007 |
45 |
0 |
0 |
T84 |
71834 |
462 |
0 |
0 |
T86 |
108962 |
1099 |
0 |
0 |
T87 |
32550 |
153 |
0 |
0 |
T94 |
14837 |
50 |
0 |
0 |
T104 |
77190 |
476 |
0 |
0 |
T133 |
20567 |
78 |
0 |
0 |
T141 |
10280 |
16 |
0 |
0 |
T142 |
108145 |
782 |
0 |
0 |
T144 |
5262 |
23 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
5676 |
0 |
0 |
T63 |
14007 |
45 |
0 |
0 |
T84 |
71834 |
629 |
0 |
0 |
T86 |
108962 |
880 |
0 |
0 |
T87 |
32550 |
161 |
0 |
0 |
T94 |
14837 |
39 |
0 |
0 |
T104 |
77190 |
508 |
0 |
0 |
T133 |
20567 |
86 |
0 |
0 |
T141 |
10280 |
59 |
0 |
0 |
T142 |
108145 |
765 |
0 |
0 |
T144 |
5262 |
1 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
6212 |
0 |
0 |
T63 |
14007 |
56 |
0 |
0 |
T84 |
71834 |
713 |
0 |
0 |
T86 |
108962 |
688 |
0 |
0 |
T87 |
32550 |
166 |
0 |
0 |
T94 |
14837 |
56 |
0 |
0 |
T104 |
77190 |
459 |
0 |
0 |
T133 |
20567 |
31 |
0 |
0 |
T141 |
10280 |
76 |
0 |
0 |
T142 |
108145 |
780 |
0 |
0 |
T144 |
5262 |
18 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
5843 |
0 |
0 |
T63 |
14007 |
75 |
0 |
0 |
T84 |
71834 |
597 |
0 |
0 |
T86 |
108962 |
672 |
0 |
0 |
T87 |
32550 |
40 |
0 |
0 |
T94 |
14837 |
85 |
0 |
0 |
T104 |
77190 |
507 |
0 |
0 |
T133 |
20567 |
39 |
0 |
0 |
T141 |
10280 |
92 |
0 |
0 |
T142 |
108145 |
653 |
0 |
0 |
T144 |
5262 |
21 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
6207 |
0 |
0 |
T63 |
14007 |
12 |
0 |
0 |
T84 |
71834 |
658 |
0 |
0 |
T86 |
108962 |
727 |
0 |
0 |
T87 |
32550 |
105 |
0 |
0 |
T94 |
14837 |
55 |
0 |
0 |
T104 |
77190 |
432 |
0 |
0 |
T133 |
20567 |
101 |
0 |
0 |
T141 |
10280 |
134 |
0 |
0 |
T142 |
108145 |
623 |
0 |
0 |
T144 |
5262 |
30 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
5668 |
0 |
0 |
T63 |
14007 |
57 |
0 |
0 |
T84 |
71834 |
559 |
0 |
0 |
T86 |
108962 |
1043 |
0 |
0 |
T87 |
32550 |
121 |
0 |
0 |
T94 |
14837 |
54 |
0 |
0 |
T104 |
77190 |
496 |
0 |
0 |
T133 |
20567 |
70 |
0 |
0 |
T141 |
10280 |
49 |
0 |
0 |
T142 |
108145 |
740 |
0 |
0 |
T144 |
5262 |
42 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
6025 |
0 |
0 |
T63 |
14007 |
92 |
0 |
0 |
T84 |
71834 |
717 |
0 |
0 |
T86 |
108962 |
883 |
0 |
0 |
T87 |
32550 |
156 |
0 |
0 |
T94 |
14837 |
44 |
0 |
0 |
T104 |
77190 |
519 |
0 |
0 |
T133 |
20567 |
71 |
0 |
0 |
T141 |
10280 |
96 |
0 |
0 |
T142 |
108145 |
646 |
0 |
0 |
T144 |
5262 |
7 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
2189 |
0 |
0 |
T63 |
14007 |
25 |
0 |
0 |
T84 |
71834 |
90 |
0 |
0 |
T86 |
108962 |
182 |
0 |
0 |
T87 |
32550 |
28 |
0 |
0 |
T94 |
14837 |
23 |
0 |
0 |
T104 |
77190 |
455 |
0 |
0 |
T133 |
20567 |
54 |
0 |
0 |
T141 |
10280 |
33 |
0 |
0 |
T142 |
108145 |
209 |
0 |
0 |
T144 |
5262 |
6 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
2291 |
0 |
0 |
T63 |
14007 |
7 |
0 |
0 |
T84 |
71834 |
89 |
0 |
0 |
T86 |
108962 |
197 |
0 |
0 |
T87 |
32550 |
18 |
0 |
0 |
T94 |
14837 |
18 |
0 |
0 |
T104 |
77190 |
493 |
0 |
0 |
T133 |
20567 |
48 |
0 |
0 |
T141 |
10280 |
3 |
0 |
0 |
T142 |
108145 |
167 |
0 |
0 |
T144 |
5262 |
5 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
2328 |
0 |
0 |
T63 |
14007 |
32 |
0 |
0 |
T84 |
71834 |
139 |
0 |
0 |
T86 |
108962 |
183 |
0 |
0 |
T87 |
32550 |
28 |
0 |
0 |
T94 |
14837 |
16 |
0 |
0 |
T104 |
77190 |
508 |
0 |
0 |
T133 |
20567 |
62 |
0 |
0 |
T141 |
10280 |
27 |
0 |
0 |
T142 |
108145 |
129 |
0 |
0 |
T144 |
5262 |
4 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
2254 |
0 |
0 |
T63 |
14007 |
12 |
0 |
0 |
T84 |
71834 |
104 |
0 |
0 |
T86 |
108962 |
152 |
0 |
0 |
T87 |
32550 |
18 |
0 |
0 |
T94 |
14837 |
7 |
0 |
0 |
T104 |
77190 |
467 |
0 |
0 |
T133 |
20567 |
43 |
0 |
0 |
T141 |
10280 |
12 |
0 |
0 |
T142 |
108145 |
183 |
0 |
0 |
T144 |
5262 |
3 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
2943 |
0 |
0 |
T63 |
14007 |
28 |
0 |
0 |
T84 |
71834 |
187 |
0 |
0 |
T86 |
108962 |
316 |
0 |
0 |
T87 |
32550 |
65 |
0 |
0 |
T94 |
14837 |
37 |
0 |
0 |
T104 |
77190 |
482 |
0 |
0 |
T133 |
20567 |
40 |
0 |
0 |
T141 |
10280 |
12 |
0 |
0 |
T142 |
108145 |
278 |
0 |
0 |
T144 |
5262 |
19 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
4843 |
0 |
0 |
T29 |
642496 |
24 |
0 |
0 |
T31 |
0 |
8 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T80 |
405335 |
0 |
0 |
0 |
T125 |
0 |
72 |
0 |
0 |
T145 |
0 |
12 |
0 |
0 |
T146 |
0 |
11 |
0 |
0 |
T147 |
0 |
24 |
0 |
0 |
T148 |
0 |
9 |
0 |
0 |
T149 |
0 |
32 |
0 |
0 |
T150 |
0 |
43 |
0 |
0 |
T151 |
40235 |
0 |
0 |
0 |
T152 |
103056 |
0 |
0 |
0 |
T153 |
165965 |
0 |
0 |
0 |
T154 |
812 |
0 |
0 |
0 |
T155 |
13976 |
0 |
0 |
0 |
T156 |
112353 |
0 |
0 |
0 |
T157 |
28568 |
0 |
0 |
0 |
T158 |
37367 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
2340 |
0 |
0 |
T63 |
14007 |
7 |
0 |
0 |
T84 |
71834 |
120 |
0 |
0 |
T85 |
20181 |
4 |
0 |
0 |
T86 |
108962 |
165 |
0 |
0 |
T87 |
32550 |
44 |
0 |
0 |
T94 |
14837 |
13 |
0 |
0 |
T104 |
77190 |
484 |
0 |
0 |
T133 |
20567 |
78 |
0 |
0 |
T141 |
10280 |
16 |
0 |
0 |
T144 |
5262 |
2 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
2272 |
0 |
0 |
T63 |
14007 |
19 |
0 |
0 |
T84 |
71834 |
122 |
0 |
0 |
T86 |
108962 |
187 |
0 |
0 |
T87 |
32550 |
34 |
0 |
0 |
T94 |
14837 |
12 |
0 |
0 |
T104 |
77190 |
487 |
0 |
0 |
T133 |
20567 |
48 |
0 |
0 |
T141 |
10280 |
15 |
0 |
0 |
T142 |
108145 |
130 |
0 |
0 |
T144 |
5262 |
2 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
1958 |
0 |
0 |
T63 |
14007 |
18 |
0 |
0 |
T84 |
71834 |
67 |
0 |
0 |
T86 |
108962 |
106 |
0 |
0 |
T87 |
32550 |
27 |
0 |
0 |
T88 |
15595 |
8 |
0 |
0 |
T94 |
14837 |
17 |
0 |
0 |
T104 |
77190 |
512 |
0 |
0 |
T133 |
20567 |
21 |
0 |
0 |
T141 |
10280 |
23 |
0 |
0 |
T144 |
5262 |
9 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
2021 |
0 |
0 |
T63 |
14007 |
13 |
0 |
0 |
T84 |
71834 |
69 |
0 |
0 |
T86 |
108962 |
89 |
0 |
0 |
T87 |
32550 |
13 |
0 |
0 |
T94 |
14837 |
10 |
0 |
0 |
T104 |
77190 |
547 |
0 |
0 |
T133 |
20567 |
49 |
0 |
0 |
T141 |
10280 |
14 |
0 |
0 |
T142 |
108145 |
118 |
0 |
0 |
T144 |
5262 |
7 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
1913 |
0 |
0 |
T63 |
14007 |
1 |
0 |
0 |
T84 |
71834 |
57 |
0 |
0 |
T85 |
20181 |
8 |
0 |
0 |
T86 |
108962 |
106 |
0 |
0 |
T87 |
32550 |
18 |
0 |
0 |
T94 |
14837 |
10 |
0 |
0 |
T104 |
77190 |
488 |
0 |
0 |
T133 |
20567 |
30 |
0 |
0 |
T141 |
10280 |
28 |
0 |
0 |
T144 |
5262 |
2 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
1971 |
0 |
0 |
T63 |
14007 |
4 |
0 |
0 |
T84 |
71834 |
48 |
0 |
0 |
T86 |
108962 |
119 |
0 |
0 |
T87 |
32550 |
25 |
0 |
0 |
T94 |
14837 |
25 |
0 |
0 |
T104 |
77190 |
432 |
0 |
0 |
T133 |
20567 |
84 |
0 |
0 |
T141 |
10280 |
11 |
0 |
0 |
T142 |
108145 |
113 |
0 |
0 |
T143 |
13389 |
38 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
3077 |
0 |
0 |
T63 |
14007 |
32 |
0 |
0 |
T84 |
71834 |
263 |
0 |
0 |
T86 |
108962 |
256 |
0 |
0 |
T87 |
32550 |
46 |
0 |
0 |
T94 |
14837 |
21 |
0 |
0 |
T104 |
77190 |
554 |
0 |
0 |
T133 |
20567 |
37 |
0 |
0 |
T141 |
10280 |
11 |
0 |
0 |
T142 |
108145 |
254 |
0 |
0 |
T144 |
5262 |
8 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
1860 |
0 |
0 |
T63 |
14007 |
21 |
0 |
0 |
T84 |
71834 |
61 |
0 |
0 |
T86 |
108962 |
74 |
0 |
0 |
T87 |
32550 |
12 |
0 |
0 |
T94 |
14837 |
13 |
0 |
0 |
T104 |
77190 |
465 |
0 |
0 |
T133 |
20567 |
64 |
0 |
0 |
T141 |
10280 |
18 |
0 |
0 |
T142 |
108145 |
109 |
0 |
0 |
T144 |
5262 |
5 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
3032 |
0 |
0 |
T63 |
14007 |
21 |
0 |
0 |
T84 |
71834 |
211 |
0 |
0 |
T86 |
108962 |
233 |
0 |
0 |
T87 |
32550 |
39 |
0 |
0 |
T94 |
14837 |
39 |
0 |
0 |
T104 |
77190 |
464 |
0 |
0 |
T133 |
20567 |
46 |
0 |
0 |
T141 |
10280 |
46 |
0 |
0 |
T142 |
108145 |
340 |
0 |
0 |
T144 |
5262 |
5 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
2366 |
0 |
0 |
T63 |
14007 |
6 |
0 |
0 |
T84 |
71834 |
116 |
0 |
0 |
T86 |
108962 |
162 |
0 |
0 |
T87 |
32550 |
30 |
0 |
0 |
T94 |
14837 |
11 |
0 |
0 |
T104 |
77190 |
554 |
0 |
0 |
T133 |
20567 |
68 |
0 |
0 |
T141 |
10280 |
28 |
0 |
0 |
T142 |
108145 |
152 |
0 |
0 |
T144 |
5262 |
9 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
1889 |
0 |
0 |
T63 |
14007 |
18 |
0 |
0 |
T84 |
71834 |
69 |
0 |
0 |
T86 |
108962 |
106 |
0 |
0 |
T87 |
32550 |
21 |
0 |
0 |
T94 |
14837 |
17 |
0 |
0 |
T104 |
77190 |
503 |
0 |
0 |
T133 |
20567 |
66 |
0 |
0 |
T141 |
10280 |
15 |
0 |
0 |
T142 |
108145 |
94 |
0 |
0 |
T143 |
13389 |
87 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
2045 |
0 |
0 |
T63 |
14007 |
6 |
0 |
0 |
T84 |
71834 |
69 |
0 |
0 |
T85 |
20181 |
7 |
0 |
0 |
T86 |
108962 |
102 |
0 |
0 |
T87 |
32550 |
11 |
0 |
0 |
T94 |
14837 |
19 |
0 |
0 |
T104 |
77190 |
508 |
0 |
0 |
T133 |
20567 |
87 |
0 |
0 |
T141 |
10280 |
18 |
0 |
0 |
T144 |
5262 |
10 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
1862 |
0 |
0 |
T63 |
14007 |
13 |
0 |
0 |
T84 |
71834 |
63 |
0 |
0 |
T86 |
108962 |
130 |
0 |
0 |
T87 |
32550 |
39 |
0 |
0 |
T94 |
14837 |
9 |
0 |
0 |
T104 |
77190 |
479 |
0 |
0 |
T133 |
20567 |
62 |
0 |
0 |
T141 |
10280 |
4 |
0 |
0 |
T142 |
108145 |
92 |
0 |
0 |
T143 |
13389 |
7 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
2010 |
0 |
0 |
T63 |
14007 |
15 |
0 |
0 |
T84 |
71834 |
75 |
0 |
0 |
T86 |
108962 |
128 |
0 |
0 |
T87 |
32550 |
32 |
0 |
0 |
T94 |
14837 |
22 |
0 |
0 |
T104 |
77190 |
499 |
0 |
0 |
T133 |
20567 |
48 |
0 |
0 |
T141 |
10280 |
25 |
0 |
0 |
T142 |
108145 |
121 |
0 |
0 |
T144 |
5262 |
9 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
1671 |
0 |
0 |
T63 |
14007 |
21 |
0 |
0 |
T84 |
71834 |
82 |
0 |
0 |
T86 |
108962 |
92 |
0 |
0 |
T87 |
32550 |
19 |
0 |
0 |
T94 |
14837 |
15 |
0 |
0 |
T104 |
77190 |
422 |
0 |
0 |
T133 |
20567 |
31 |
0 |
0 |
T141 |
10280 |
11 |
0 |
0 |
T142 |
108145 |
78 |
0 |
0 |
T144 |
5262 |
16 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442449040 |
1864 |
0 |
0 |
T63 |
14007 |
24 |
0 |
0 |
T84 |
71834 |
71 |
0 |
0 |
T86 |
108962 |
119 |
0 |
0 |
T87 |
32550 |
13 |
0 |
0 |
T94 |
14837 |
13 |
0 |
0 |
T104 |
77190 |
503 |
0 |
0 |
T133 |
20567 |
67 |
0 |
0 |
T141 |
10280 |
9 |
0 |
0 |
T142 |
108145 |
112 |
0 |
0 |
T144 |
5262 |
5 |
0 |
0 |