Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3294476	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4116753

1

T1

878

T2

1007

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4021884	1			T1	2		T2	306		T3	1
values[0x0]	1693251	1			T1	445		T2	447		T3	2
values[0x1]	1696094	1			T1	435		T2	443		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2347584	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5063645

1

T1

879

T2

1047

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	35950	1			T1	1		T4	50		T8	59
valid_sources[0x01]	51338	1			T1	3		T2	9		T4	59
valid_sources[0x02]	26573	1			T3	1		T4	47		T5	1
valid_sources[0x03]	25952	1			T1	9		T4	41		T8	38
valid_sources[0x04]	27360	1			T2	75		T4	57		T8	12
valid_sources[0x05]	31073	1			T4	65		T8	19		T12	42
valid_sources[0x06]	28700	1			T4	55		T6	1		T8	26
valid_sources[0x07]	26648	1			T4	60		T8	19		T12	55
valid_sources[0x08]	25643	1			T4	52		T8	70		T12	40
valid_sources[0x09]	29515	1			T1	2		T2	18		T4	61
valid_sources[0x0a]	27624	1			T4	32		T5	1		T8	32
valid_sources[0x0b]	32664	1			T4	60		T8	62		T11	2479
valid_sources[0x0c]	41417	1			T1	5		T4	65		T8	86
valid_sources[0x0d]	33210	1			T1	1		T4	63		T8	23
valid_sources[0x0e]	26199	1			T1	8		T4	55		T8	43
valid_sources[0x0f]	29321	1			T4	56		T8	73		T12	45
valid_sources[0x10]	36419	1			T1	1		T4	48		T8	50
valid_sources[0x11]	28627	1			T4	70		T8	39		T12	64
valid_sources[0x12]	27822	1			T1	4		T4	72		T6	1
valid_sources[0x13]	35879	1			T1	3		T4	50		T8	42
valid_sources[0x14]	26015	1			T4	46		T8	34		T12	49
valid_sources[0x15]	24967	1			T4	61		T8	50		T9	1
valid_sources[0x16]	25863	1			T4	43		T8	26		T12	39
valid_sources[0x17]	27772	1			T1	5		T4	33		T8	20
valid_sources[0x18]	31195	1			T1	2		T4	63		T8	52
valid_sources[0x19]	29028	1			T4	50		T5	1		T8	48
valid_sources[0x1a]	30277	1			T2	14		T4	48		T8	55
valid_sources[0x1b]	25223	1			T2	69		T4	48		T8	17
valid_sources[0x1c]	26518	1			T1	7		T4	70		T5	1
valid_sources[0x1d]	32867	1			T1	13		T4	46		T8	40
valid_sources[0x1e]	30816	1			T4	82		T8	10		T12	69
valid_sources[0x1f]	27487	1			T1	11		T4	60		T8	60
valid_sources[0x20]	29664	1			T1	5		T2	3		T4	48
valid_sources[0x21]	28549	1			T1	2		T4	55		T8	46
valid_sources[0x22]	24461	1			T1	13		T4	42		T8	21
valid_sources[0x23]	25211	1			T4	49		T8	30		T12	26
valid_sources[0x24]	25592	1			T1	1		T4	49		T8	26
valid_sources[0x25]	25624	1			T1	15		T4	46		T8	28
valid_sources[0x26]	30761	1			T1	3		T4	49		T5	1
valid_sources[0x27]	26299	1			T1	1		T2	53		T4	38
valid_sources[0x28]	28204	1			T4	67		T8	13		T12	37
valid_sources[0x29]	27746	1			T1	8		T4	61		T5	1
valid_sources[0x2a]	26971	1			T4	44		T5	1		T8	19
valid_sources[0x2b]	27898	1			T1	5		T4	58		T8	40
valid_sources[0x2c]	30750	1			T1	5		T4	52		T8	46
valid_sources[0x2d]	28403	1			T2	15		T4	37		T8	73
valid_sources[0x2e]	29900	1			T4	59		T8	35		T9	2
valid_sources[0x2f]	28497	1			T1	4		T4	39		T8	45
valid_sources[0x30]	34394	1			T1	8		T4	44		T8	89
valid_sources[0x31]	28016	1			T4	58		T8	12		T12	69
valid_sources[0x32]	25701	1			T4	45		T8	41		T12	41
valid_sources[0x33]	28727	1			T1	17		T4	55		T8	53
valid_sources[0x34]	27234	1			T1	4		T4	38		T8	65
valid_sources[0x35]	30004	1			T1	7		T4	56		T6	1
valid_sources[0x36]	36153	1			T1	4		T2	7		T4	47
valid_sources[0x37]	29548	1			T4	47		T8	52		T12	46
valid_sources[0x38]	26906	1			T1	14		T4	39		T8	31
valid_sources[0x39]	32539	1			T4	41		T8	53		T12	54
valid_sources[0x3a]	28459	1			T4	75		T8	36		T12	51
valid_sources[0x3b]	27111	1			T4	60		T6	1		T8	102
valid_sources[0x3c]	28245	1			T2	55		T4	48		T8	84
valid_sources[0x3d]	27031	1			T1	4		T4	52		T8	55
valid_sources[0x3e]	29490	1			T4	41		T8	65		T12	53
valid_sources[0x3f]	27141	1			T4	57		T8	23		T12	52
valid_sources[0x40]	28512	1			T4	41		T8	110		T12	61
valid_sources[0x41]	30502	1			T2	43		T4	43		T8	29
valid_sources[0x42]	28450	1			T1	9		T4	50		T8	32
valid_sources[0x43]	29926	1			T1	1		T4	53		T8	83
valid_sources[0x44]	30493	1			T4	42		T8	78		T12	69
valid_sources[0x45]	29311	1			T1	2		T4	41		T8	79
valid_sources[0x46]	28545	1			T1	1		T4	70		T8	25
valid_sources[0x47]	26834	1			T1	1		T4	58		T8	40
valid_sources[0x48]	27949	1			T1	12		T2	6		T4	52
valid_sources[0x49]	28635	1			T1	5		T4	75		T8	46
valid_sources[0x4a]	26123	1			T4	51		T8	46		T12	76
valid_sources[0x4b]	31701	1			T4	54		T8	20		T12	40
valid_sources[0x4c]	28577	1			T1	8		T2	44		T4	57
valid_sources[0x4d]	28566	1			T4	53		T5	1		T6	1
valid_sources[0x4e]	27077	1			T1	9		T4	62		T8	35
valid_sources[0x4f]	28079	1			T4	46		T8	37		T12	72
valid_sources[0x50]	26029	1			T4	45		T8	81		T12	54
valid_sources[0x51]	29944	1			T1	8		T4	62		T8	24
valid_sources[0x52]	28224	1			T1	1		T2	13		T4	42
valid_sources[0x53]	27470	1			T3	1		T4	29		T5	2
valid_sources[0x54]	27715	1			T1	3		T4	47		T8	42
valid_sources[0x55]	27740	1			T1	4		T4	51		T8	28
valid_sources[0x56]	25651	1			T4	40		T8	79		T12	62
valid_sources[0x57]	34368	1			T1	2		T4	53		T8	35
valid_sources[0x58]	27941	1			T1	6		T4	52		T8	58
valid_sources[0x59]	26494	1			T4	56		T8	33		T12	46
valid_sources[0x5a]	25729	1			T4	47		T5	1		T8	22
valid_sources[0x5b]	26046	1			T1	3		T4	64		T8	74
valid_sources[0x5c]	31341	1			T1	5		T4	39		T8	36
valid_sources[0x5d]	45224	1			T1	5		T4	45		T8	35
valid_sources[0x5e]	28287	1			T4	61		T8	44		T12	47
valid_sources[0x5f]	27235	1			T1	1		T4	65		T8	31
valid_sources[0x60]	26964	1			T4	43		T8	67		T12	47
valid_sources[0x61]	29909	1			T4	50		T8	38		T12	26
valid_sources[0x62]	35774	1			T2	34		T4	57		T5	1
valid_sources[0x63]	29192	1			T1	11		T4	58		T8	31
valid_sources[0x64]	29322	1			T1	8		T4	55		T8	13
valid_sources[0x65]	30783	1			T1	15		T4	50		T8	33
valid_sources[0x66]	42199	1			T1	8		T4	38		T7	4108
valid_sources[0x67]	32319	1			T4	38		T8	39		T12	66
valid_sources[0x68]	29444	1			T4	57		T8	56		T12	47
valid_sources[0x69]	29455	1			T1	3		T4	51		T8	42
valid_sources[0x6a]	26931	1			T1	8		T4	67		T6	1
valid_sources[0x6b]	29644	1			T1	1		T4	81		T5	3
valid_sources[0x6c]	30722	1			T4	53		T8	40		T12	45
valid_sources[0x6d]	28785	1			T4	40		T8	28		T12	33
valid_sources[0x6e]	29178	1			T4	54		T6	1		T8	52
valid_sources[0x6f]	26834	1			T4	49		T8	58		T12	76
valid_sources[0x70]	26853	1			T4	48		T8	92		T12	66
valid_sources[0x71]	27407	1			T1	2		T4	45		T8	36
valid_sources[0x72]	29289	1			T4	41		T5	1		T8	51
valid_sources[0x73]	31165	1			T4	55		T8	39		T12	58
valid_sources[0x74]	30268	1			T1	9		T4	42		T8	40
valid_sources[0x75]	27430	1			T4	59		T5	1		T6	1
valid_sources[0x76]	31315	1			T1	1		T4	50		T8	33
valid_sources[0x77]	25354	1			T2	46		T4	41		T8	42
valid_sources[0x78]	29493	1			T1	1		T2	10		T4	46
valid_sources[0x79]	38666	1			T1	15		T4	46		T8	53
valid_sources[0x7a]	29016	1			T4	44		T8	30		T12	55
valid_sources[0x7b]	26111	1			T1	17		T2	30		T4	44
valid_sources[0x7c]	26978	1			T1	8		T3	1		T4	60
valid_sources[0x7d]	28901	1			T4	46		T8	22		T12	73
valid_sources[0x7e]	31809	1			T1	5		T4	52		T8	31
valid_sources[0x7f]	26177	1			T4	50		T6	1		T8	10
valid_sources[0x80]	30576	1			T1	2		T4	39		T8	37

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1034928

1

T1

1

T2

129

T4

926

values[0x0]

all_enables

biggest_size

1552229

1

T1

443

T2

445

T3

1

values[0x1]

all_enables

biggest_size

1529596

1

T1

434

T2

433

T4

4647