Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3316124

1

T1

4

T2

189

T3

3

full_word

4117883

1

T1

878

T2

1007

T3

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7433547	1			T1	882		T2	1196		T3	4
auto[TlIntgErrCmd]	164	1			T80	4		T110	4		T111	12
auto[TlIntgErrData]	131	1			T80	2		T110	2		T111	8
auto[TlIntgErrBoth]	165	1			T80	4		T110	4		T111	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4025314

1

T1

2

T2

306

T3

1

auto[1]

3408693

1

T1

880

T2

890

T3

3

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2989926	1			T1	1		T2	177		T3	1
auto[TlIntgErrNone]	partial	auto[1]	325784	1			T1	3		T2	12		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	1035170	1			T1	1		T2	129		T4	926
auto[TlIntgErrNone]	full_word	auto[1]	3082667	1			T1	877		T2	878		T3	1
auto[TlIntgErrCmd]	partial	auto[0]	68	1			T80	1		T110	1		T111	6
auto[TlIntgErrCmd]	partial	auto[1]	78	1			T80	3		T110	3		T111	5
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T111	1		T180	1		T182	2
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T181	1		T185	1		T186	1
auto[TlIntgErrData]	partial	auto[0]	55	1			T80	2		T111	1		T180	7
auto[TlIntgErrData]	partial	auto[1]	60	1			T110	1		T111	4		T180	5
auto[TlIntgErrData]	full_word	auto[0]	9	1			T110	1		T111	3		T180	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T181	2		T186	1		T187	1
auto[TlIntgErrBoth]	partial	auto[0]	75	1			T80	2		T110	1		T111	5
auto[TlIntgErrBoth]	partial	auto[1]	78	1			T80	2		T110	2		T111	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T110	1		T111	1		T180	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T186	1		T184	3		T188	2