Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	449864034	2858799	0	0
DepthKnown_A	449864034	449730213	0	0
RvalidKnown_A	449864034	449730213	0	0
WreadyKnown_A	449864034	449730213	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	2858799	0	0
T1	3083	1671	0	0
T2	12283	832	0	0
T3	1100	0	0	0
T4	393735	14150	0	0
T5	951	0	0	0
T6	2287	0	0	0
T7	249719	1663	0	0
T8	302939	832	0	0
T9	2946	0	0	0
T10	1832	0	0	0
T11	0	1663	0	0
T12	0	14979	0	0
T13	0	1667	0	0
T14	0	1854	0	0
T15	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	449730213	0	0
T1	3083	3005	0	0
T2	12283	12203	0	0
T3	1100	1041	0	0
T4	393735	393548	0	0
T5	951	862	0	0
T6	2287	2221	0	0
T7	249719	249628	0	0
T8	302939	302841	0	0
T9	2946	2866	0	0
T10	1832	1732	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	449730213	0	0
T1	3083	3005	0	0
T2	12283	12203	0	0
T3	1100	1041	0	0
T4	393735	393548	0	0
T5	951	862	0	0
T6	2287	2221	0	0
T7	249719	249628	0	0
T8	302939	302841	0	0
T9	2946	2866	0	0
T10	1832	1732	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	449730213	0	0
T1	3083	3005	0	0
T2	12283	12203	0	0
T3	1100	1041	0	0
T4	393735	393548	0	0
T5	951	862	0	0
T6	2287	2221	0	0
T7	249719	249628	0	0
T8	302939	302841	0	0
T9	2946	2866	0	0
T10	1832	1732	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	449864034	3302662	0	0
DepthKnown_A	449864034	449730213	0	0
RvalidKnown_A	449864034	449730213	0	0
WreadyKnown_A	449864034	449730213	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	3302662	0	0
T1	3083	840	0	0
T2	12283	832	0	0
T3	1100	0	0	0
T4	393735	10295	0	0
T5	951	0	0	0
T6	2287	0	0	0
T7	249719	832	0	0
T8	302939	832	0	0
T9	2946	0	0	0
T10	1832	0	0	0
T11	0	832	0	0
T12	0	27156	0	0
T13	0	836	0	0
T14	0	1344	0	0
T15	0	3696	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	449730213	0	0
T1	3083	3005	0	0
T2	12283	12203	0	0
T3	1100	1041	0	0
T4	393735	393548	0	0
T5	951	862	0	0
T6	2287	2221	0	0
T7	249719	249628	0	0
T8	302939	302841	0	0
T9	2946	2866	0	0
T10	1832	1732	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	449730213	0	0
T1	3083	3005	0	0
T2	12283	12203	0	0
T3	1100	1041	0	0
T4	393735	393548	0	0
T5	951	862	0	0
T6	2287	2221	0	0
T7	249719	249628	0	0
T8	302939	302841	0	0
T9	2946	2866	0	0
T10	1832	1732	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	449730213	0	0
T1	3083	3005	0	0
T2	12283	12203	0	0
T3	1100	1041	0	0
T4	393735	393548	0	0
T5	951	862	0	0
T6	2287	2221	0	0
T7	249719	249628	0	0
T8	302939	302841	0	0
T9	2946	2866	0	0
T10	1832	1732	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	449864034	189396	0	0
DepthKnown_A	449864034	449730213	0	0
RvalidKnown_A	449864034	449730213	0	0
WreadyKnown_A	449864034	449730213	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	189396	0	0
T4	393735	580	0	0
T5	951	0	0	0
T6	2287	0	0	0
T7	249719	0	0	0
T8	302939	0	0	0
T9	2946	0	0	0
T10	1832	1	0	0
T11	109198	0	0	0
T12	111182	432	0	0
T13	45287	0	0	0
T18	0	827	0	0
T28	0	842	0	0
T29	0	1178	0	0
T30	0	563	0	0
T31	0	687	0	0
T39	0	545	0	0
T40	0	164	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	449730213	0	0
T1	3083	3005	0	0
T2	12283	12203	0	0
T3	1100	1041	0	0
T4	393735	393548	0	0
T5	951	862	0	0
T6	2287	2221	0	0
T7	249719	249628	0	0
T8	302939	302841	0	0
T9	2946	2866	0	0
T10	1832	1732	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	449730213	0	0
T1	3083	3005	0	0
T2	12283	12203	0	0
T3	1100	1041	0	0
T4	393735	393548	0	0
T5	951	862	0	0
T6	2287	2221	0	0
T7	249719	249628	0	0
T8	302939	302841	0	0
T9	2946	2866	0	0
T10	1832	1732	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	449730213	0	0
T1	3083	3005	0	0
T2	12283	12203	0	0
T3	1100	1041	0	0
T4	393735	393548	0	0
T5	951	862	0	0
T6	2287	2221	0	0
T7	249719	249628	0	0
T8	302939	302841	0	0
T9	2946	2866	0	0
T10	1832	1732	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	449864034	453107	0	0
DepthKnown_A	449864034	449730213	0	0
RvalidKnown_A	449864034	449730213	0	0
WreadyKnown_A	449864034	449730213	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	453107	0	0
T4	393735	2236	0	0
T5	951	0	0	0
T6	2287	0	0	0
T7	249719	0	0	0
T8	302939	0	0	0
T9	2946	0	0	0
T10	1832	1	0	0
T11	109198	0	0	0
T12	111182	2019	0	0
T13	45287	0	0	0
T18	0	827	0	0
T28	0	842	0	0
T29	0	3730	0	0
T30	0	563	0	0
T31	0	2042	0	0
T39	0	545	0	0
T40	0	164	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	449730213	0	0
T1	3083	3005	0	0
T2	12283	12203	0	0
T3	1100	1041	0	0
T4	393735	393548	0	0
T5	951	862	0	0
T6	2287	2221	0	0
T7	249719	249628	0	0
T8	302939	302841	0	0
T9	2946	2866	0	0
T10	1832	1732	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	449730213	0	0
T1	3083	3005	0	0
T2	12283	12203	0	0
T3	1100	1041	0	0
T4	393735	393548	0	0
T5	951	862	0	0
T6	2287	2221	0	0
T7	249719	249628	0	0
T8	302939	302841	0	0
T9	2946	2866	0	0
T10	1832	1732	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	449730213	0	0
T1	3083	3005	0	0
T2	12283	12203	0	0
T3	1100	1041	0	0
T4	393735	393548	0	0
T5	951	862	0	0
T6	2287	2221	0	0
T7	249719	249628	0	0
T8	302939	302841	0	0
T9	2946	2866	0	0
T10	1832	1732	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	449864034	5756180	0	0
DepthKnown_A	449864034	449730213	0	0
RvalidKnown_A	449864034	449730213	0	0
WreadyKnown_A	449864034	449730213	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	5756180	0	0
T1	3083	50	0	0
T2	12283	364	0	0
T3	1100	4	0	0
T4	393735	6110	0	0
T5	951	55	0	0
T6	2287	29	0	0
T7	249719	9635	0	0
T8	302939	10925	0	0
T9	2946	16	0	0
T10	1832	51	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	449730213	0	0
T1	3083	3005	0	0
T2	12283	12203	0	0
T3	1100	1041	0	0
T4	393735	393548	0	0
T5	951	862	0	0
T6	2287	2221	0	0
T7	249719	249628	0	0
T8	302939	302841	0	0
T9	2946	2866	0	0
T10	1832	1732	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	449730213	0	0
T1	3083	3005	0	0
T2	12283	12203	0	0
T3	1100	1041	0	0
T4	393735	393548	0	0
T5	951	862	0	0
T6	2287	2221	0	0
T7	249719	249628	0	0
T8	302939	302841	0	0
T9	2946	2866	0	0
T10	1832	1732	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	449730213	0	0
T1	3083	3005	0	0
T2	12283	12203	0	0
T3	1100	1041	0	0
T4	393735	393548	0	0
T5	951	862	0	0
T6	2287	2221	0	0
T7	249719	249628	0	0
T8	302939	302841	0	0
T9	2946	2866	0	0
T10	1832	1732	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	449864034	11338492	0	0
DepthKnown_A	449864034	449730213	0	0
RvalidKnown_A	449864034	449730213	0	0
WreadyKnown_A	449864034	449730213	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	11338492	0	0
T1	3083	249	0	0
T2	12283	364	0	0
T3	1100	4	0	0
T4	393735	23301	0	0
T5	951	55	0	0
T6	2287	29	0	0
T7	249719	9634	0	0
T8	302939	10925	0	0
T9	2946	16	0	0
T10	1832	51	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	449730213	0	0
T1	3083	3005	0	0
T2	12283	12203	0	0
T3	1100	1041	0	0
T4	393735	393548	0	0
T5	951	862	0	0
T6	2287	2221	0	0
T7	249719	249628	0	0
T8	302939	302841	0	0
T9	2946	2866	0	0
T10	1832	1732	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	449730213	0	0
T1	3083	3005	0	0
T2	12283	12203	0	0
T3	1100	1041	0	0
T4	393735	393548	0	0
T5	951	862	0	0
T6	2287	2221	0	0
T7	249719	249628	0	0
T8	302939	302841	0	0
T9	2946	2866	0	0
T10	1832	1732	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449864034	449730213	0	0
T1	3083	3005	0	0
T2	12283	12203	0	0
T3	1100	1041	0	0
T4	393735	393548	0	0
T5	951	862	0	0
T6	2287	2221	0	0
T7	249719	249628	0	0
T8	302939	302841	0	0
T9	2946	2866	0	0
T10	1832	1732	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0