Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T10,T18
1	0	Covered	T4,T10,T18

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T10
1	0	Unreachable
1	1	Covered	T4,T10,T18

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T12,T39

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T39
1	0	Covered	T4,T12,T39

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Unreachable
1	1	Covered	T4,T12,T39

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T12,T18

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T10,T12
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	753857861	599235037	0	0
CheckNGreaterZero_A	2865	2865	0	0
GntImpliesReady_A	753857861	3853864	0	0
GntImpliesValid_A	753857861	3853864	0	0
GrantKnown_A	753857861	599235037	0	0
IdxKnown_A	753857861	599235037	0	0
IndexIsCorrect_A	753857861	3853864	0	0
LockArbDecision_A	753857861	0	0	0
NoReadyValidNoGrant_A	753857861	0	0	0
ReadyAndValidImplyGrant_A	753857861	3853864	0	0
ReqAndReadyImplyGrant_A	753857861	3853864	0	0
ReqImpliesValid_A	753857861	3853864	0	0
ReqStaysHighUntilGranted0_M	753857861	0	0	0
RoundRobin_A	753857861	6	0	955
ValidKnown_A	753857861	599235037	0	0
gen_data_port_assertion.DataFlow_A	753857861	3853864	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	753857861	599235037	0	0
T1	3083	3005	0	0
T2	32504	32424	0	0
T3	1100	1041	0	0
T4	1773277	1078736	0	0
T5	951	862	0	0
T6	3583	2869	0	0
T7	331799	290668	0	0
T8	501759	402073	0	0
T9	2946	2866	0	0
T10	3352	2492	0	0
T11	106138	52672	0	0
T12	1013574	504485	0	0
T13	16736	8368	0	0
T14	65034	32517	0	0
T15	3226	0	0	0
T18	0	121016	0	0
T28	0	154576	0	0
T29	0	296792	0	0
T30	0	85736	0	0
T31	0	49240	0	0
T32	0	78784	0	0
T33	0	30216	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2865	2865	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	753857861	3853864	0	0
T1	3083	832	0	0
T2	12283	832	0	0
T3	1100	0	0	0
T4	1773277	13588	0	0
T5	951	0	0	0
T6	3583	0	0	0
T7	331799	832	0	0
T8	501759	832	0	0
T9	2946	0	0	0
T10	3352	32	0	0
T11	106138	832	0	0
T12	1013574	12580	0	0
T13	16736	832	0	0
T14	65034	1344	0	0
T15	6452	0	0	0
T18	0	4930	0	0
T20	0	8324	0	0
T28	0	4443	0	0
T29	0	7302	0	0
T30	0	3153	0	0
T31	0	5398	0	0
T39	0	17121	0	0
T40	0	1192	0	0
T43	0	7181	0	0
T59	0	1944	0	0
T60	0	4529	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	753857861	3853864	0	0
T1	3083	832	0	0
T2	12283	832	0	0
T3	1100	0	0	0
T4	1773277	13588	0	0
T5	951	0	0	0
T6	3583	0	0	0
T7	331799	832	0	0
T8	501759	832	0	0
T9	2946	0	0	0
T10	3352	32	0	0
T11	106138	832	0	0
T12	1013574	12580	0	0
T13	16736	832	0	0
T14	65034	1344	0	0
T15	6452	0	0	0
T18	0	4930	0	0
T20	0	8324	0	0
T28	0	4443	0	0
T29	0	7302	0	0
T30	0	3153	0	0
T31	0	5398	0	0
T39	0	17121	0	0
T40	0	1192	0	0
T43	0	7181	0	0
T59	0	1944	0	0
T60	0	4529	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	753857861	599235037	0	0
T1	3083	3005	0	0
T2	32504	32424	0	0
T3	1100	1041	0	0
T4	1773277	1078736	0	0
T5	951	862	0	0
T6	3583	2869	0	0
T7	331799	290668	0	0
T8	501759	402073	0	0
T9	2946	2866	0	0
T10	3352	2492	0	0
T11	106138	52672	0	0
T12	1013574	504485	0	0
T13	16736	8368	0	0
T14	65034	32517	0	0
T15	3226	0	0	0
T18	0	121016	0	0
T28	0	154576	0	0
T29	0	296792	0	0
T30	0	85736	0	0
T31	0	49240	0	0
T32	0	78784	0	0
T33	0	30216	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	753857861	599235037	0	0
T1	3083	3005	0	0
T2	32504	32424	0	0
T3	1100	1041	0	0
T4	1773277	1078736	0	0
T5	951	862	0	0
T6	3583	2869	0	0
T7	331799	290668	0	0
T8	501759	402073	0	0
T9	2946	2866	0	0
T10	3352	2492	0	0
T11	106138	52672	0	0
T12	1013574	504485	0	0
T13	16736	8368	0	0
T14	65034	32517	0	0
T15	3226	0	0	0
T18	0	121016	0	0
T28	0	154576	0	0
T29	0	296792	0	0
T30	0	85736	0	0
T31	0	49240	0	0
T32	0	78784	0	0
T33	0	30216	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	753857861	3853864	0	0
T1	3083	832	0	0
T2	12283	832	0	0
T3	1100	0	0	0
T4	1773277	13588	0	0
T5	951	0	0	0
T6	3583	0	0	0
T7	331799	832	0	0
T8	501759	832	0	0
T9	2946	0	0	0
T10	3352	32	0	0
T11	106138	832	0	0
T12	1013574	12580	0	0
T13	16736	832	0	0
T14	65034	1344	0	0
T15	6452	0	0	0
T18	0	4930	0	0
T20	0	8324	0	0
T28	0	4443	0	0
T29	0	7302	0	0
T30	0	3153	0	0
T31	0	5398	0	0
T39	0	17121	0	0
T40	0	1192	0	0
T43	0	7181	0	0
T59	0	1944	0	0
T60	0	4529	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	753857861	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	753857861	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	753857861	3853864	0	0
T1	3083	832	0	0
T2	12283	832	0	0
T3	1100	0	0	0
T4	1773277	13588	0	0
T5	951	0	0	0
T6	3583	0	0	0
T7	331799	832	0	0
T8	501759	832	0	0
T9	2946	0	0	0
T10	3352	32	0	0
T11	106138	832	0	0
T12	1013574	12580	0	0
T13	16736	832	0	0
T14	65034	1344	0	0
T15	6452	0	0	0
T18	0	4930	0	0
T20	0	8324	0	0
T28	0	4443	0	0
T29	0	7302	0	0
T30	0	3153	0	0
T31	0	5398	0	0
T39	0	17121	0	0
T40	0	1192	0	0
T43	0	7181	0	0
T59	0	1944	0	0
T60	0	4529	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	753857861	3853864	0	0
T1	3083	832	0	0
T2	12283	832	0	0
T3	1100	0	0	0
T4	1773277	13588	0	0
T5	951	0	0	0
T6	3583	0	0	0
T7	331799	832	0	0
T8	501759	832	0	0
T9	2946	0	0	0
T10	3352	32	0	0
T11	106138	832	0	0
T12	1013574	12580	0	0
T13	16736	832	0	0
T14	65034	1344	0	0
T15	6452	0	0	0
T18	0	4930	0	0
T20	0	8324	0	0
T28	0	4443	0	0
T29	0	7302	0	0
T30	0	3153	0	0
T31	0	5398	0	0
T39	0	17121	0	0
T40	0	1192	0	0
T43	0	7181	0	0
T59	0	1944	0	0
T60	0	4529	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	753857861	3853864	0	0
T1	3083	832	0	0
T2	12283	832	0	0
T3	1100	0	0	0
T4	1773277	13588	0	0
T5	951	0	0	0
T6	3583	0	0	0
T7	331799	832	0	0
T8	501759	832	0	0
T9	2946	0	0	0
T10	3352	32	0	0
T11	106138	832	0	0
T12	1013574	12580	0	0
T13	16736	832	0	0
T14	65034	1344	0	0
T15	6452	0	0	0
T18	0	4930	0	0
T20	0	8324	0	0
T28	0	4443	0	0
T29	0	7302	0	0
T30	0	3153	0	0
T31	0	5398	0	0
T39	0	17121	0	0
T40	0	1192	0	0
T43	0	7181	0	0
T59	0	1944	0	0
T60	0	4529	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	753857861	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	753857861	6	0	955
T22	124451	1	0	1
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	7870	0	0	1
T67	1672	0	0	1
T68	17019	0	0	1
T69	780661	0	0	1
T70	336508	0	0	1
T71	349641	0	0	1
T72	54355	0	0	1
T73	11268	0	0	1
T74	9788	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	753857861	599235037	0	0
T1	3083	3005	0	0
T2	32504	32424	0	0
T3	1100	1041	0	0
T4	1773277	1078736	0	0
T5	951	862	0	0
T6	3583	2869	0	0
T7	331799	290668	0	0
T8	501759	402073	0	0
T9	2946	2866	0	0
T10	3352	2492	0	0
T11	106138	52672	0	0
T12	1013574	504485	0	0
T13	16736	8368	0	0
T14	65034	32517	0	0
T15	3226	0	0	0
T18	0	121016	0	0
T28	0	154576	0	0
T29	0	296792	0	0
T30	0	85736	0	0
T31	0	49240	0	0
T32	0	78784	0	0
T33	0	30216	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	753857861	3853864	0	0
T1	3083	832	0	0
T2	12283	832	0	0
T3	1100	0	0	0
T4	1773277	13588	0	0
T5	951	0	0	0
T6	3583	0	0	0
T7	331799	832	0	0
T8	501759	832	0	0
T9	2946	0	0	0
T10	3352	32	0	0
T11	106138	832	0	0
T12	1013574	12580	0	0
T13	16736	832	0	0
T14	65034	1344	0	0
T15	6452	0	0	0
T18	0	4930	0	0
T20	0	8324	0	0
T28	0	4443	0	0
T29	0	7302	0	0
T30	0	3153	0	0
T31	0	5398	0	0
T39	0	17121	0	0
T40	0	1192	0	0
T43	0	7181	0	0
T59	0	1944	0	0
T60	0	4529	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T10,T18
1	0	Covered	T4,T10,T18

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T10
1	0	Unreachable
1	1	Covered	T4,T10,T18

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T10,T18
0	0	1	Unreachable
0	0	0	Covered	T4,T6,T10

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T18
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153217377	29146889	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	153217377	619048	0	0
GntImpliesValid_A	153217377	619048	0	0
GrantKnown_A	153217377	29146889	0	0
IdxKnown_A	153217377	29146889	0	0
IndexIsCorrect_A	153217377	619048	0	0
LockArbDecision_A	153217377	0	0	0
NoReadyValidNoGrant_A	153217377	0	0	0
ReadyAndValidImplyGrant_A	153217377	619048	0	0
ReqAndReadyImplyGrant_A	153217377	619048	0	0
ReqImpliesValid_A	153217377	619048	0	0
ReqStaysHighUntilGranted0_M	153217377	0	0	0
RoundRobin_A	153217377	0	0	0
ValidKnown_A	153217377	29146889	0	0
gen_data_port_assertion.DataFlow_A	153217377	619048	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	29146889	0	0
T4	689771	109376	0	0
T6	648	648	0	0
T7	41040	0	0	0
T8	99410	0	0	0
T10	760	760	0	0
T11	53069	0	0	0
T12	506787	0	0	0
T13	8368	0	0	0
T14	32517	0	0	0
T15	3226	0	0	0
T18	0	121016	0	0
T28	0	154576	0	0
T29	0	296792	0	0
T30	0	85736	0	0
T31	0	49240	0	0
T32	0	78784	0	0
T33	0	30216	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	619048	0	0
T4	689771	1501	0	0
T6	648	0	0	0
T7	41040	0	0	0
T8	99410	0	0	0
T10	760	18	0	0
T11	53069	0	0	0
T12	506787	0	0	0
T13	8368	0	0	0
T14	32517	0	0	0
T15	3226	0	0	0
T18	0	4930	0	0
T20	0	1331	0	0
T28	0	4443	0	0
T29	0	7302	0	0
T30	0	3153	0	0
T31	0	1561	0	0
T43	0	2582	0	0
T59	0	1944	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	619048	0	0
T4	689771	1501	0	0
T6	648	0	0	0
T7	41040	0	0	0
T8	99410	0	0	0
T10	760	18	0	0
T11	53069	0	0	0
T12	506787	0	0	0
T13	8368	0	0	0
T14	32517	0	0	0
T15	3226	0	0	0
T18	0	4930	0	0
T20	0	1331	0	0
T28	0	4443	0	0
T29	0	7302	0	0
T30	0	3153	0	0
T31	0	1561	0	0
T43	0	2582	0	0
T59	0	1944	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	29146889	0	0
T4	689771	109376	0	0
T6	648	648	0	0
T7	41040	0	0	0
T8	99410	0	0	0
T10	760	760	0	0
T11	53069	0	0	0
T12	506787	0	0	0
T13	8368	0	0	0
T14	32517	0	0	0
T15	3226	0	0	0
T18	0	121016	0	0
T28	0	154576	0	0
T29	0	296792	0	0
T30	0	85736	0	0
T31	0	49240	0	0
T32	0	78784	0	0
T33	0	30216	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	29146889	0	0
T4	689771	109376	0	0
T6	648	648	0	0
T7	41040	0	0	0
T8	99410	0	0	0
T10	760	760	0	0
T11	53069	0	0	0
T12	506787	0	0	0
T13	8368	0	0	0
T14	32517	0	0	0
T15	3226	0	0	0
T18	0	121016	0	0
T28	0	154576	0	0
T29	0	296792	0	0
T30	0	85736	0	0
T31	0	49240	0	0
T32	0	78784	0	0
T33	0	30216	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	619048	0	0
T4	689771	1501	0	0
T6	648	0	0	0
T7	41040	0	0	0
T8	99410	0	0	0
T10	760	18	0	0
T11	53069	0	0	0
T12	506787	0	0	0
T13	8368	0	0	0
T14	32517	0	0	0
T15	3226	0	0	0
T18	0	4930	0	0
T20	0	1331	0	0
T28	0	4443	0	0
T29	0	7302	0	0
T30	0	3153	0	0
T31	0	1561	0	0
T43	0	2582	0	0
T59	0	1944	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	619048	0	0
T4	689771	1501	0	0
T6	648	0	0	0
T7	41040	0	0	0
T8	99410	0	0	0
T10	760	18	0	0
T11	53069	0	0	0
T12	506787	0	0	0
T13	8368	0	0	0
T14	32517	0	0	0
T15	3226	0	0	0
T18	0	4930	0	0
T20	0	1331	0	0
T28	0	4443	0	0
T29	0	7302	0	0
T30	0	3153	0	0
T31	0	1561	0	0
T43	0	2582	0	0
T59	0	1944	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	619048	0	0
T4	689771	1501	0	0
T6	648	0	0	0
T7	41040	0	0	0
T8	99410	0	0	0
T10	760	18	0	0
T11	53069	0	0	0
T12	506787	0	0	0
T13	8368	0	0	0
T14	32517	0	0	0
T15	3226	0	0	0
T18	0	4930	0	0
T20	0	1331	0	0
T28	0	4443	0	0
T29	0	7302	0	0
T30	0	3153	0	0
T31	0	1561	0	0
T43	0	2582	0	0
T59	0	1944	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	619048	0	0
T4	689771	1501	0	0
T6	648	0	0	0
T7	41040	0	0	0
T8	99410	0	0	0
T10	760	18	0	0
T11	53069	0	0	0
T12	506787	0	0	0
T13	8368	0	0	0
T14	32517	0	0	0
T15	3226	0	0	0
T18	0	4930	0	0
T20	0	1331	0	0
T28	0	4443	0	0
T29	0	7302	0	0
T30	0	3153	0	0
T31	0	1561	0	0
T43	0	2582	0	0
T59	0	1944	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	29146889	0	0
T4	689771	109376	0	0
T6	648	648	0	0
T7	41040	0	0	0
T8	99410	0	0	0
T10	760	760	0	0
T11	53069	0	0	0
T12	506787	0	0	0
T13	8368	0	0	0
T14	32517	0	0	0
T15	3226	0	0	0
T18	0	121016	0	0
T28	0	154576	0	0
T29	0	296792	0	0
T30	0	85736	0	0
T31	0	49240	0	0
T32	0	78784	0	0
T33	0	30216	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	619048	0	0
T4	689771	1501	0	0
T6	648	0	0	0
T7	41040	0	0	0
T8	99410	0	0	0
T10	760	18	0	0
T11	53069	0	0	0
T12	506787	0	0	0
T13	8368	0	0	0
T14	32517	0	0	0
T15	3226	0	0	0
T18	0	4930	0	0
T20	0	1331	0	0
T28	0	4443	0	0
T29	0	7302	0	0
T30	0	3153	0	0
T31	0	1561	0	0
T43	0	2582	0	0
T59	0	1944	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T12,T39

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T39
1	0	Covered	T4,T12,T39

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Unreachable
1	1	Covered	T4,T12,T39

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T39
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T12,T39
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T39
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T39
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153217377	122750048	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	153217377	978752	0	0
GntImpliesValid_A	153217377	978752	0	0
GrantKnown_A	153217377	122750048	0	0
IdxKnown_A	153217377	122750048	0	0
IndexIsCorrect_A	153217377	978752	0	0
LockArbDecision_A	153217377	0	0	0
NoReadyValidNoGrant_A	153217377	0	0	0
ReadyAndValidImplyGrant_A	153217377	978752	0	0
ReqAndReadyImplyGrant_A	153217377	978752	0	0
ReqImpliesValid_A	153217377	978752	0	0
ReqStaysHighUntilGranted0_M	153217377	0	0	0
RoundRobin_A	153217377	0	0	0
ValidKnown_A	153217377	122750048	0	0
gen_data_port_assertion.DataFlow_A	153217377	978752	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	122750048	0	0
T2	20221	20221	0	0
T4	689771	575812	0	0
T6	648	0	0	0
T7	41040	41040	0	0
T8	99410	99232	0	0
T10	760	0	0	0
T11	53069	52672	0	0
T12	506787	504485	0	0
T13	8368	8368	0	0
T14	32517	32517	0	0
T15	0	3226	0	0
T16	0	85200	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	978752	0	0
T4	689771	3626	0	0
T6	648	0	0	0
T7	41040	0	0	0
T8	99410	0	0	0
T10	760	0	0	0
T11	53069	0	0	0
T12	506787	2143	0	0
T13	8368	0	0	0
T14	32517	0	0	0
T15	3226	0	0	0
T20	0	6993	0	0
T31	0	3837	0	0
T39	0	17121	0	0
T40	0	1192	0	0
T42	0	937	0	0
T43	0	4599	0	0
T49	0	2	0	0
T60	0	4529	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	978752	0	0
T4	689771	3626	0	0
T6	648	0	0	0
T7	41040	0	0	0
T8	99410	0	0	0
T10	760	0	0	0
T11	53069	0	0	0
T12	506787	2143	0	0
T13	8368	0	0	0
T14	32517	0	0	0
T15	3226	0	0	0
T20	0	6993	0	0
T31	0	3837	0	0
T39	0	17121	0	0
T40	0	1192	0	0
T42	0	937	0	0
T43	0	4599	0	0
T49	0	2	0	0
T60	0	4529	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	122750048	0	0
T2	20221	20221	0	0
T4	689771	575812	0	0
T6	648	0	0	0
T7	41040	41040	0	0
T8	99410	99232	0	0
T10	760	0	0	0
T11	53069	52672	0	0
T12	506787	504485	0	0
T13	8368	8368	0	0
T14	32517	32517	0	0
T15	0	3226	0	0
T16	0	85200	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	122750048	0	0
T2	20221	20221	0	0
T4	689771	575812	0	0
T6	648	0	0	0
T7	41040	41040	0	0
T8	99410	99232	0	0
T10	760	0	0	0
T11	53069	52672	0	0
T12	506787	504485	0	0
T13	8368	8368	0	0
T14	32517	32517	0	0
T15	0	3226	0	0
T16	0	85200	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	978752	0	0
T4	689771	3626	0	0
T6	648	0	0	0
T7	41040	0	0	0
T8	99410	0	0	0
T10	760	0	0	0
T11	53069	0	0	0
T12	506787	2143	0	0
T13	8368	0	0	0
T14	32517	0	0	0
T15	3226	0	0	0
T20	0	6993	0	0
T31	0	3837	0	0
T39	0	17121	0	0
T40	0	1192	0	0
T42	0	937	0	0
T43	0	4599	0	0
T49	0	2	0	0
T60	0	4529	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	978752	0	0
T4	689771	3626	0	0
T6	648	0	0	0
T7	41040	0	0	0
T8	99410	0	0	0
T10	760	0	0	0
T11	53069	0	0	0
T12	506787	2143	0	0
T13	8368	0	0	0
T14	32517	0	0	0
T15	3226	0	0	0
T20	0	6993	0	0
T31	0	3837	0	0
T39	0	17121	0	0
T40	0	1192	0	0
T42	0	937	0	0
T43	0	4599	0	0
T49	0	2	0	0
T60	0	4529	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	978752	0	0
T4	689771	3626	0	0
T6	648	0	0	0
T7	41040	0	0	0
T8	99410	0	0	0
T10	760	0	0	0
T11	53069	0	0	0
T12	506787	2143	0	0
T13	8368	0	0	0
T14	32517	0	0	0
T15	3226	0	0	0
T20	0	6993	0	0
T31	0	3837	0	0
T39	0	17121	0	0
T40	0	1192	0	0
T42	0	937	0	0
T43	0	4599	0	0
T49	0	2	0	0
T60	0	4529	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	978752	0	0
T4	689771	3626	0	0
T6	648	0	0	0
T7	41040	0	0	0
T8	99410	0	0	0
T10	760	0	0	0
T11	53069	0	0	0
T12	506787	2143	0	0
T13	8368	0	0	0
T14	32517	0	0	0
T15	3226	0	0	0
T20	0	6993	0	0
T31	0	3837	0	0
T39	0	17121	0	0
T40	0	1192	0	0
T42	0	937	0	0
T43	0	4599	0	0
T49	0	2	0	0
T60	0	4529	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	122750048	0	0
T2	20221	20221	0	0
T4	689771	575812	0	0
T6	648	0	0	0
T7	41040	41040	0	0
T8	99410	99232	0	0
T10	760	0	0	0
T11	53069	52672	0	0
T12	506787	504485	0	0
T13	8368	8368	0	0
T14	32517	32517	0	0
T15	0	3226	0	0
T16	0	85200	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153217377	978752	0	0
T4	689771	3626	0	0
T6	648	0	0	0
T7	41040	0	0	0
T8	99410	0	0	0
T10	760	0	0	0
T11	53069	0	0	0
T12	506787	2143	0	0
T13	8368	0	0	0
T14	32517	0	0	0
T15	3226	0	0	0
T20	0	6993	0	0
T31	0	3837	0	0
T39	0	17121	0	0
T40	0	1192	0	0
T42	0	937	0	0
T43	0	4599	0	0
T49	0	2	0	0
T60	0	4529	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T12,T18

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T10,T12
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	447423107	447338100	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	447423107	2256064	0	0
GntImpliesValid_A	447423107	2256064	0	0
GrantKnown_A	447423107	447338100	0	0
IdxKnown_A	447423107	447338100	0	0
IndexIsCorrect_A	447423107	2256064	0	0
LockArbDecision_A	447423107	0	0	0
NoReadyValidNoGrant_A	447423107	0	0	0
ReadyAndValidImplyGrant_A	447423107	2256064	0	0
ReqAndReadyImplyGrant_A	447423107	2256064	0	0
ReqImpliesValid_A	447423107	2256064	0	0
ReqStaysHighUntilGranted0_M	447423107	0	0	0
RoundRobin_A	447423107	6	0	955
ValidKnown_A	447423107	447338100	0	0
gen_data_port_assertion.DataFlow_A	447423107	2256064	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447423107	447338100	0	0
T1	3083	3005	0	0
T2	12283	12203	0	0
T3	1100	1041	0	0
T4	393735	393548	0	0
T5	951	862	0	0
T6	2287	2221	0	0
T7	249719	249628	0	0
T8	302939	302841	0	0
T9	2946	2866	0	0
T10	1832	1732	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447423107	2256064	0	0
T1	3083	832	0	0
T2	12283	832	0	0
T3	1100	0	0	0
T4	393735	8461	0	0
T5	951	0	0	0
T6	2287	0	0	0
T7	249719	832	0	0
T8	302939	832	0	0
T9	2946	0	0	0
T10	1832	14	0	0
T11	0	832	0	0
T12	0	10437	0	0
T13	0	832	0	0
T14	0	1344	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447423107	2256064	0	0
T1	3083	832	0	0
T2	12283	832	0	0
T3	1100	0	0	0
T4	393735	8461	0	0
T5	951	0	0	0
T6	2287	0	0	0
T7	249719	832	0	0
T8	302939	832	0	0
T9	2946	0	0	0
T10	1832	14	0	0
T11	0	832	0	0
T12	0	10437	0	0
T13	0	832	0	0
T14	0	1344	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447423107	447338100	0	0
T1	3083	3005	0	0
T2	12283	12203	0	0
T3	1100	1041	0	0
T4	393735	393548	0	0
T5	951	862	0	0
T6	2287	2221	0	0
T7	249719	249628	0	0
T8	302939	302841	0	0
T9	2946	2866	0	0
T10	1832	1732	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447423107	447338100	0	0
T1	3083	3005	0	0
T2	12283	12203	0	0
T3	1100	1041	0	0
T4	393735	393548	0	0
T5	951	862	0	0
T6	2287	2221	0	0
T7	249719	249628	0	0
T8	302939	302841	0	0
T9	2946	2866	0	0
T10	1832	1732	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447423107	2256064	0	0
T1	3083	832	0	0
T2	12283	832	0	0
T3	1100	0	0	0
T4	393735	8461	0	0
T5	951	0	0	0
T6	2287	0	0	0
T7	249719	832	0	0
T8	302939	832	0	0
T9	2946	0	0	0
T10	1832	14	0	0
T11	0	832	0	0
T12	0	10437	0	0
T13	0	832	0	0
T14	0	1344	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447423107	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447423107	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447423107	2256064	0	0
T1	3083	832	0	0
T2	12283	832	0	0
T3	1100	0	0	0
T4	393735	8461	0	0
T5	951	0	0	0
T6	2287	0	0	0
T7	249719	832	0	0
T8	302939	832	0	0
T9	2946	0	0	0
T10	1832	14	0	0
T11	0	832	0	0
T12	0	10437	0	0
T13	0	832	0	0
T14	0	1344	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447423107	2256064	0	0
T1	3083	832	0	0
T2	12283	832	0	0
T3	1100	0	0	0
T4	393735	8461	0	0
T5	951	0	0	0
T6	2287	0	0	0
T7	249719	832	0	0
T8	302939	832	0	0
T9	2946	0	0	0
T10	1832	14	0	0
T11	0	832	0	0
T12	0	10437	0	0
T13	0	832	0	0
T14	0	1344	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447423107	2256064	0	0
T1	3083	832	0	0
T2	12283	832	0	0
T3	1100	0	0	0
T4	393735	8461	0	0
T5	951	0	0	0
T6	2287	0	0	0
T7	249719	832	0	0
T8	302939	832	0	0
T9	2946	0	0	0
T10	1832	14	0	0
T11	0	832	0	0
T12	0	10437	0	0
T13	0	832	0	0
T14	0	1344	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	447423107	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447423107	6	0	955
T22	124451	1	0	1
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	7870	0	0	1
T67	1672	0	0	1
T68	17019	0	0	1
T69	780661	0	0	1
T70	336508	0	0	1
T71	349641	0	0	1
T72	54355	0	0	1
T73	11268	0	0	1
T74	9788	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447423107	447338100	0	0
T1	3083	3005	0	0
T2	12283	12203	0	0
T3	1100	1041	0	0
T4	393735	393548	0	0
T5	951	862	0	0
T6	2287	2221	0	0
T7	249719	249628	0	0
T8	302939	302841	0	0
T9	2946	2866	0	0
T10	1832	1732	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447423107	2256064	0	0
T1	3083	832	0	0
T2	12283	832	0	0
T3	1100	0	0	0
T4	393735	8461	0	0
T5	951	0	0	0
T6	2287	0	0	0
T7	249719	832	0	0
T8	302939	832	0	0
T9	2946	0	0	0
T10	1832	14	0	0
T11	0	832	0	0
T12	0	10437	0	0
T13	0	832	0	0
T14	0	1344	0	0