Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3286363	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3983155

1

T1

10357

T2

3434

T3

1059

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3944644	1			T1	18987		T2	2817		T3	337
values[0x0]	1661772	1			T1	452		T2	1653		T3	423
values[0x1]	1663102	1			T1	432		T2	1585		T3	480

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2333448	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4936070

1

T1

12256

T2

4187

T3

1097

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30807	1			T1	59		T3	4		T4	58
valid_sources[0x01]	26667	1			T1	56		T3	1		T4	57
valid_sources[0x02]	28516	1			T1	80		T2	3		T3	2
valid_sources[0x03]	25119	1			T1	73		T2	6		T3	2
valid_sources[0x04]	29983	1			T1	72		T3	1		T4	51
valid_sources[0x05]	46119	1			T1	74		T2	3		T3	8
valid_sources[0x06]	26290	1			T1	56		T3	12		T4	54
valid_sources[0x07]	31881	1			T1	78		T3	2		T4	74
valid_sources[0x08]	31574	1			T1	108		T3	1		T4	51
valid_sources[0x09]	30271	1			T1	68		T2	4		T3	8
valid_sources[0x0a]	26455	1			T1	75		T3	7		T4	55
valid_sources[0x0b]	26009	1			T1	78		T3	7		T4	73
valid_sources[0x0c]	28373	1			T1	90		T2	132		T3	9
valid_sources[0x0d]	25634	1			T1	72		T2	3		T3	6
valid_sources[0x0e]	25923	1			T1	60		T2	1		T3	1
valid_sources[0x0f]	27377	1			T1	64		T3	4		T4	48
valid_sources[0x10]	32623	1			T1	74		T3	8		T4	62
valid_sources[0x11]	28391	1			T1	82		T3	5		T4	50
valid_sources[0x12]	29560	1			T1	88		T2	227		T3	8
valid_sources[0x13]	25775	1			T1	86		T3	6		T4	60
valid_sources[0x14]	33894	1			T1	85		T2	3		T3	3
valid_sources[0x15]	26856	1			T1	97		T4	35		T5	2
valid_sources[0x16]	27994	1			T1	71		T3	9		T4	68
valid_sources[0x17]	31358	1			T1	99		T3	3		T4	76
valid_sources[0x18]	25439	1			T1	73		T2	34		T3	2
valid_sources[0x19]	26786	1			T1	71		T2	131		T3	6
valid_sources[0x1a]	33309	1			T1	88		T2	85		T3	8
valid_sources[0x1b]	26344	1			T1	89		T2	403		T3	6
valid_sources[0x1c]	28406	1			T1	76		T3	7		T4	77
valid_sources[0x1d]	27344	1			T1	74		T2	42		T3	1
valid_sources[0x1e]	27114	1			T1	80		T3	1		T4	76
valid_sources[0x1f]	29377	1			T1	65		T3	2		T4	52
valid_sources[0x20]	28303	1			T1	95		T3	11		T4	50
valid_sources[0x21]	26706	1			T1	92		T3	10		T4	79
valid_sources[0x22]	29933	1			T1	76		T3	3		T4	78
valid_sources[0x23]	26108	1			T1	85		T3	1		T4	62
valid_sources[0x24]	29548	1			T1	79		T3	7		T4	55
valid_sources[0x25]	27444	1			T1	89		T3	6		T4	50
valid_sources[0x26]	27854	1			T1	56		T3	2		T4	40
valid_sources[0x27]	31345	1			T1	66		T3	3		T4	55
valid_sources[0x28]	29170	1			T1	70		T3	8		T4	72
valid_sources[0x29]	28261	1			T1	61		T2	4		T3	5
valid_sources[0x2a]	27535	1			T1	94		T3	4		T4	64
valid_sources[0x2b]	28481	1			T1	99		T3	5		T4	54
valid_sources[0x2c]	27312	1			T1	73		T2	1		T3	8
valid_sources[0x2d]	28016	1			T1	73		T2	1		T3	4
valid_sources[0x2e]	29210	1			T1	87		T3	2		T4	68
valid_sources[0x2f]	26253	1			T1	66		T2	2		T3	1
valid_sources[0x30]	26947	1			T1	80		T3	3		T4	67
valid_sources[0x31]	31244	1			T1	77		T3	8		T4	68
valid_sources[0x32]	29288	1			T1	71		T3	8		T4	53
valid_sources[0x33]	29270	1			T1	71		T3	3		T4	65
valid_sources[0x34]	29219	1			T1	67		T2	3		T3	7
valid_sources[0x35]	25513	1			T1	82		T2	139		T3	9
valid_sources[0x36]	27829	1			T1	58		T3	12		T4	84
valid_sources[0x37]	27382	1			T1	85		T3	7		T4	64
valid_sources[0x38]	26519	1			T1	50		T3	11		T4	70
valid_sources[0x39]	26051	1			T1	95		T3	6		T4	68
valid_sources[0x3a]	25608	1			T1	87		T3	4		T4	70
valid_sources[0x3b]	29296	1			T1	68		T3	5		T4	58
valid_sources[0x3c]	24957	1			T1	81		T3	5		T4	53
valid_sources[0x3d]	28775	1			T1	87		T3	2		T4	66
valid_sources[0x3e]	31689	1			T1	100		T3	4		T4	72
valid_sources[0x3f]	29928	1			T1	79		T3	7		T4	54
valid_sources[0x40]	26606	1			T1	100		T3	3		T4	51
valid_sources[0x41]	33898	1			T1	67		T3	1		T4	79
valid_sources[0x42]	26298	1			T1	62		T3	2		T4	67
valid_sources[0x43]	27445	1			T1	65		T3	1		T4	78
valid_sources[0x44]	32760	1			T1	93		T3	4		T4	58
valid_sources[0x45]	29975	1			T1	70		T3	3		T4	59
valid_sources[0x46]	42634	1			T1	72		T2	114		T3	8
valid_sources[0x47]	25189	1			T1	57		T2	1		T3	1
valid_sources[0x48]	26415	1			T1	61		T2	31		T3	5
valid_sources[0x49]	26814	1			T1	68		T3	8		T4	76
valid_sources[0x4a]	26201	1			T1	90		T3	2		T4	67
valid_sources[0x4b]	29089	1			T1	52		T2	521		T3	4
valid_sources[0x4c]	28236	1			T1	79		T3	6		T4	67
valid_sources[0x4d]	26304	1			T1	78		T2	92		T3	6
valid_sources[0x4e]	28467	1			T1	72		T3	3		T4	57
valid_sources[0x4f]	24256	1			T1	94		T3	3		T4	63
valid_sources[0x50]	26039	1			T1	91		T3	1		T4	45
valid_sources[0x51]	27222	1			T1	70		T3	6		T4	66
valid_sources[0x52]	26501	1			T1	65		T2	4		T3	5
valid_sources[0x53]	26847	1			T1	76		T3	3		T4	50
valid_sources[0x54]	30122	1			T1	68		T2	1		T3	12
valid_sources[0x55]	28069	1			T1	93		T3	4		T4	56
valid_sources[0x56]	26423	1			T1	84		T3	1		T4	59
valid_sources[0x57]	27458	1			T1	72		T3	9		T4	67
valid_sources[0x58]	26140	1			T1	87		T3	5		T4	60
valid_sources[0x59]	31119	1			T1	85		T3	10		T4	58
valid_sources[0x5a]	24715	1			T1	75		T3	2		T4	79
valid_sources[0x5b]	26948	1			T1	79		T3	6		T4	55
valid_sources[0x5c]	27053	1			T1	61		T2	355		T3	5
valid_sources[0x5d]	26849	1			T1	72		T3	3		T4	64
valid_sources[0x5e]	25228	1			T1	54		T2	1		T3	7
valid_sources[0x5f]	26606	1			T1	53		T2	46		T3	8
valid_sources[0x60]	24407	1			T1	72		T3	6		T4	70
valid_sources[0x61]	30688	1			T1	72		T3	1		T4	57
valid_sources[0x62]	26662	1			T1	72		T3	2		T4	53
valid_sources[0x63]	27440	1			T1	76		T2	2		T3	5
valid_sources[0x64]	29142	1			T1	90		T3	5		T4	60
valid_sources[0x65]	27995	1			T1	75		T4	70		T6	70
valid_sources[0x66]	29522	1			T1	86		T3	5		T4	71
valid_sources[0x67]	25009	1			T1	95		T3	2		T4	78
valid_sources[0x68]	30619	1			T1	70		T3	3		T4	81
valid_sources[0x69]	27796	1			T1	75		T2	4		T3	3
valid_sources[0x6a]	34661	1			T1	69		T3	1		T4	61
valid_sources[0x6b]	28278	1			T1	75		T3	7		T4	56
valid_sources[0x6c]	26139	1			T1	75		T3	7		T4	45
valid_sources[0x6d]	25643	1			T1	94		T2	155		T3	5
valid_sources[0x6e]	29831	1			T1	78		T3	2		T4	55
valid_sources[0x6f]	29287	1			T1	58		T3	3		T4	56
valid_sources[0x70]	29645	1			T1	62		T3	5		T4	60
valid_sources[0x71]	29005	1			T1	83		T2	71		T3	7
valid_sources[0x72]	30122	1			T1	96		T2	3		T3	4
valid_sources[0x73]	27352	1			T1	110		T2	5		T3	3
valid_sources[0x74]	27786	1			T1	84		T4	80		T5	9
valid_sources[0x75]	26623	1			T1	86		T2	305		T3	3
valid_sources[0x76]	29265	1			T1	80		T3	5		T4	73
valid_sources[0x77]	28648	1			T1	95		T3	4		T4	74
valid_sources[0x78]	26617	1			T1	92		T2	4		T3	2
valid_sources[0x79]	26959	1			T1	56		T2	2		T3	3
valid_sources[0x7a]	32383	1			T1	66		T3	5		T4	77
valid_sources[0x7b]	29186	1			T1	81		T2	2		T3	7
valid_sources[0x7c]	26197	1			T1	86		T3	2		T4	56
valid_sources[0x7d]	31645	1			T1	89		T3	2		T4	77
valid_sources[0x7e]	35293	1			T1	75		T2	2		T3	3
valid_sources[0x7f]	27016	1			T1	90		T3	9		T4	64
valid_sources[0x80]	24318	1			T1	59		T2	1		T3	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

964628

1

T1

9476

T2

1046

T3

165

values[0x0]

all_enables

biggest_size

1519877

1

T1

451

T2

1262

T3

422

values[0x1]

all_enables

biggest_size

1498650

1

T1

430

T2

1126

T3

472