Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3308526

1

T1

9514

T2

2621

T3

181

full_word

3984478

1

T1

10357

T2

3434

T3

1059

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7292624	1			T1	19871		T2	6055		T3	1240
auto[TlIntgErrCmd]	130	1			T65	9		T66	2		T95	4
auto[TlIntgErrData]	129	1			T65	4		T66	2		T95	4
auto[TlIntgErrBoth]	121	1			T65	7		T66	6		T95	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3948315

1

T1

18987

T2

2817

T3

337

auto[1]

3344689

1

T1

884

T2

3238

T3

903

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2983242	1			T1	9511		T2	1771		T3	172
auto[TlIntgErrNone]	partial	auto[1]	324937	1			T1	3		T2	850		T3	9
auto[TlIntgErrNone]	full_word	auto[0]	964909	1			T1	9476		T2	1046		T3	165
auto[TlIntgErrNone]	full_word	auto[1]	3019536	1			T1	881		T2	2388		T3	894
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T65	4		T66	1		T95	1
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T65	5		T66	1		T95	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T180	1		T181	1		T178	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T109	1		T182	1		T183	1
auto[TlIntgErrData]	partial	auto[0]	61	1			T65	1		T66	2		T95	2
auto[TlIntgErrData]	partial	auto[1]	57	1			T65	2		T95	2		T110	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T65	1		T109	1		T178	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T110	1		T183	1		T181	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T65	1		T66	1		T107	3
auto[TlIntgErrBoth]	partial	auto[1]	72	1			T65	5		T66	4		T95	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T65	1		T184	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T66	1		T180	2		T185	1