Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	437003399	2739704	0	0
DepthKnown_A	437003399	436874385	0	0
RvalidKnown_A	437003399	436874385	0	0
WreadyKnown_A	437003399	436874385	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	2739704	0	0
T1	419661	1667	0	0
T2	149231	0	0	0
T3	13034	1665	0	0
T4	350534	1343	0	0
T5	100505	1663	0	0
T6	558351	3707	0	0
T7	9380	832	0	0
T8	8019	832	0	0
T9	354565	14158	0	0
T10	385277	0	0	0
T11	0	832	0	0
T12	0	14969	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	436874385	0	0
T1	419661	419578	0	0
T2	149231	149166	0	0
T3	13034	12960	0	0
T4	350534	350468	0	0
T5	100505	100448	0	0
T6	558351	558275	0	0
T7	9380	9301	0	0
T8	8019	7929	0	0
T9	354565	354497	0	0
T10	385277	385195	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	436874385	0	0
T1	419661	419578	0	0
T2	149231	149166	0	0
T3	13034	12960	0	0
T4	350534	350468	0	0
T5	100505	100448	0	0
T6	558351	558275	0	0
T7	9380	9301	0	0
T8	8019	7929	0	0
T9	354565	354497	0	0
T10	385277	385195	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	436874385	0	0
T1	419661	419578	0	0
T2	149231	149166	0	0
T3	13034	12960	0	0
T4	350534	350468	0	0
T5	100505	100448	0	0
T6	558351	558275	0	0
T7	9380	9301	0	0
T8	8019	7929	0	0
T9	354565	354497	0	0
T10	385277	385195	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	437003399	3001728	0	0
DepthKnown_A	437003399	436874385	0	0
RvalidKnown_A	437003399	436874385	0	0
WreadyKnown_A	437003399	436874385	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	3001728	0	0
T1	419661	836	0	0
T2	149231	0	0	0
T3	13034	836	0	0
T4	350534	1088	0	0
T5	100505	832	0	0
T6	558351	1856	0	0
T7	9380	2522	0	0
T8	8019	832	0	0
T9	354565	26477	0	0
T10	385277	0	0	0
T11	0	832	0	0
T12	0	9152	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	436874385	0	0
T1	419661	419578	0	0
T2	149231	149166	0	0
T3	13034	12960	0	0
T4	350534	350468	0	0
T5	100505	100448	0	0
T6	558351	558275	0	0
T7	9380	9301	0	0
T8	8019	7929	0	0
T9	354565	354497	0	0
T10	385277	385195	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	436874385	0	0
T1	419661	419578	0	0
T2	149231	149166	0	0
T3	13034	12960	0	0
T4	350534	350468	0	0
T5	100505	100448	0	0
T6	558351	558275	0	0
T7	9380	9301	0	0
T8	8019	7929	0	0
T9	354565	354497	0	0
T10	385277	385195	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	436874385	0	0
T1	419661	419578	0	0
T2	149231	149166	0	0
T3	13034	12960	0	0
T4	350534	350468	0	0
T5	100505	100448	0	0
T6	558351	558275	0	0
T7	9380	9301	0	0
T8	8019	7929	0	0
T9	354565	354497	0	0
T10	385277	385195	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	437003399	174723	0	0
DepthKnown_A	437003399	436874385	0	0
RvalidKnown_A	437003399	436874385	0	0
WreadyKnown_A	437003399	436874385	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	174723	0	0
T2	149231	855	0	0
T3	13034	0	0	0
T4	350534	0	0	0
T5	100505	0	0	0
T6	558351	0	0	0
T7	9380	0	0	0
T8	8019	0	0	0
T9	354565	563	0	0
T10	385277	0	0	0
T12	0	96	0	0
T30	3453	28	0	0
T31	0	521	0	0
T33	0	802	0	0
T34	0	893	0	0
T39	0	128	0	0
T40	0	128	0	0
T41	0	617	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	436874385	0	0
T1	419661	419578	0	0
T2	149231	149166	0	0
T3	13034	12960	0	0
T4	350534	350468	0	0
T5	100505	100448	0	0
T6	558351	558275	0	0
T7	9380	9301	0	0
T8	8019	7929	0	0
T9	354565	354497	0	0
T10	385277	385195	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	436874385	0	0
T1	419661	419578	0	0
T2	149231	149166	0	0
T3	13034	12960	0	0
T4	350534	350468	0	0
T5	100505	100448	0	0
T6	558351	558275	0	0
T7	9380	9301	0	0
T8	8019	7929	0	0
T9	354565	354497	0	0
T10	385277	385195	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	436874385	0	0
T1	419661	419578	0	0
T2	149231	149166	0	0
T3	13034	12960	0	0
T4	350534	350468	0	0
T5	100505	100448	0	0
T6	558351	558275	0	0
T7	9380	9301	0	0
T8	8019	7929	0	0
T9	354565	354497	0	0
T10	385277	385195	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	437003399	383361	0	0
DepthKnown_A	437003399	436874385	0	0
RvalidKnown_A	437003399	436874385	0	0
WreadyKnown_A	437003399	436874385	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	383361	0	0
T2	149231	3895	0	0
T3	13034	0	0	0
T4	350534	0	0	0
T5	100505	0	0	0
T6	558351	0	0	0
T7	9380	0	0	0
T8	8019	0	0	0
T9	354565	1736	0	0
T10	385277	0	0	0
T12	0	96	0	0
T30	3453	28	0	0
T31	0	521	0	0
T33	0	802	0	0
T34	0	893	0	0
T39	0	379	0	0
T40	0	128	0	0
T41	0	617	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	436874385	0	0
T1	419661	419578	0	0
T2	149231	149166	0	0
T3	13034	12960	0	0
T4	350534	350468	0	0
T5	100505	100448	0	0
T6	558351	558275	0	0
T7	9380	9301	0	0
T8	8019	7929	0	0
T9	354565	354497	0	0
T10	385277	385195	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	436874385	0	0
T1	419661	419578	0	0
T2	149231	149166	0	0
T3	13034	12960	0	0
T4	350534	350468	0	0
T5	100505	100448	0	0
T6	558351	558275	0	0
T7	9380	9301	0	0
T8	8019	7929	0	0
T9	354565	354497	0	0
T10	385277	385195	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	436874385	0	0
T1	419661	419578	0	0
T2	149231	149166	0	0
T3	13034	12960	0	0
T4	350534	350468	0	0
T5	100505	100448	0	0
T6	558351	558275	0	0
T7	9380	9301	0	0
T8	8019	7929	0	0
T9	354565	354497	0	0
T10	385277	385195	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	437003399	5623634	0	0
DepthKnown_A	437003399	436874385	0	0
RvalidKnown_A	437003399	436874385	0	0
WreadyKnown_A	437003399	436874385	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	5623634	0	0
T1	419661	19046	0	0
T2	149231	5782	0	0
T3	13034	413	0	0
T4	350534	15074	0	0
T5	100505	61	0	0
T6	558351	17888	0	0
T7	9380	47	0	0
T8	8019	301	0	0
T9	354565	1845	0	0
T10	385277	481	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	436874385	0	0
T1	419661	419578	0	0
T2	149231	149166	0	0
T3	13034	12960	0	0
T4	350534	350468	0	0
T5	100505	100448	0	0
T6	558351	558275	0	0
T7	9380	9301	0	0
T8	8019	7929	0	0
T9	354565	354497	0	0
T10	385277	385195	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	436874385	0	0
T1	419661	419578	0	0
T2	149231	149166	0	0
T3	13034	12960	0	0
T4	350534	350468	0	0
T5	100505	100448	0	0
T6	558351	558275	0	0
T7	9380	9301	0	0
T8	8019	7929	0	0
T9	354565	354497	0	0
T10	385277	385195	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	436874385	0	0
T1	419661	419578	0	0
T2	149231	149166	0	0
T3	13034	12960	0	0
T4	350534	350468	0	0
T5	100505	100448	0	0
T6	558351	558275	0	0
T7	9380	9301	0	0
T8	8019	7929	0	0
T9	354565	354497	0	0
T10	385277	385195	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	437003399	10728432	0	0
DepthKnown_A	437003399	436874385	0	0
RvalidKnown_A	437003399	436874385	0	0
WreadyKnown_A	437003399	436874385	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	10728432	0	0
T1	419661	82732	0	0
T2	149231	23236	0	0
T3	13034	1790	0	0
T4	350534	15080	0	0
T5	100505	61	0	0
T6	558351	17888	0	0
T7	9380	144	0	0
T8	8019	301	0	0
T9	354565	5441	0	0
T10	385277	481	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	436874385	0	0
T1	419661	419578	0	0
T2	149231	149166	0	0
T3	13034	12960	0	0
T4	350534	350468	0	0
T5	100505	100448	0	0
T6	558351	558275	0	0
T7	9380	9301	0	0
T8	8019	7929	0	0
T9	354565	354497	0	0
T10	385277	385195	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	436874385	0	0
T1	419661	419578	0	0
T2	149231	149166	0	0
T3	13034	12960	0	0
T4	350534	350468	0	0
T5	100505	100448	0	0
T6	558351	558275	0	0
T7	9380	9301	0	0
T8	8019	7929	0	0
T9	354565	354497	0	0
T10	385277	385195	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437003399	436874385	0	0
T1	419661	419578	0	0
T2	149231	149166	0	0
T3	13034	12960	0	0
T4	350534	350468	0	0
T5	100505	100448	0	0
T6	558351	558275	0	0
T7	9380	9301	0	0
T8	8019	7929	0	0
T9	354565	354497	0	0
T10	385277	385195	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0