Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T30,T31
1	0	Covered	T2,T30,T31

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T30
1	0	Unreachable
1	1	Covered	T2,T30,T31

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T11,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T11,T12
1	0	Covered	T9,T11,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T9,T11,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T9,T30

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T30
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T30
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	717370883	574657583	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	717370883	3500155	0	0
GntImpliesValid_A	717370883	3500155	0	0
GrantKnown_A	717370883	574657583	0	0
IdxKnown_A	717370883	574657583	0	0
IndexIsCorrect_A	717370883	3500155	0	0
LockArbDecision_A	717370883	0	0	0
NoReadyValidNoGrant_A	717370883	0	0	0
ReadyAndValidImplyGrant_A	717370883	3500155	0	0
ReqAndReadyImplyGrant_A	717370883	3500155	0	0
ReqImpliesValid_A	717370883	3500155	0	0
ReqStaysHighUntilGranted0_M	717370883	0	0	0
RoundRobin_A	717370883	3	0	956
ValidKnown_A	717370883	574657583	0	0
gen_data_port_assertion.DataFlow_A	717370883	3500155	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717370883	574657583	0	0
T1	471681	471598	0	0
T2	1068643	603382	0	0
T3	48490	30688	0	0
T4	489568	419985	0	0
T5	150169	124794	0	0
T6	717059	637629	0	0
T7	9700	9461	0	0
T8	11587	9713	0	0
T9	2287283	1316442	0	0
T10	495701	439107	0	0
T11	0	28714	0	0
T12	0	397833	0	0
T13	0	102368	0	0
T22	0	1312	0	0
T24	0	308784	0	0
T25	0	119880	0	0
T30	2032	2032	0	0
T31	0	66480	0	0
T33	0	37760	0	0
T34	0	158240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717370883	3500155	0	0
T1	419661	832	0	0
T2	608937	7239	0	0
T3	30762	832	0	0
T4	420051	1088	0	0
T5	125337	832	0	0
T6	637705	1856	0	0
T7	9540	832	0	0
T8	9803	832	0	0
T9	2287283	20564	0	0
T10	495701	0	0	0
T11	28760	3	0	0
T12	401837	400	0	0
T13	0	8716	0	0
T22	0	105	0	0
T24	0	4983	0	0
T25	0	4566	0	0
T27	0	116	0	0
T30	4064	184	0	0
T31	70620	2839	0	0
T33	115915	11383	0	0
T34	0	4943	0	0
T40	139736	1028	0	0
T41	274091	0	0	0
T44	129766	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717370883	3500155	0	0
T1	419661	832	0	0
T2	608937	7239	0	0
T3	30762	832	0	0
T4	420051	1088	0	0
T5	125337	832	0	0
T6	637705	1856	0	0
T7	9540	832	0	0
T8	9803	832	0	0
T9	2287283	20564	0	0
T10	495701	0	0	0
T11	28760	3	0	0
T12	401837	400	0	0
T13	0	8716	0	0
T22	0	105	0	0
T24	0	4983	0	0
T25	0	4566	0	0
T27	0	116	0	0
T30	4064	184	0	0
T31	70620	2839	0	0
T33	115915	11383	0	0
T34	0	4943	0	0
T40	139736	1028	0	0
T41	274091	0	0	0
T44	129766	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717370883	574657583	0	0
T1	471681	471598	0	0
T2	1068643	603382	0	0
T3	48490	30688	0	0
T4	489568	419985	0	0
T5	150169	124794	0	0
T6	717059	637629	0	0
T7	9700	9461	0	0
T8	11587	9713	0	0
T9	2287283	1316442	0	0
T10	495701	439107	0	0
T11	0	28714	0	0
T12	0	397833	0	0
T13	0	102368	0	0
T22	0	1312	0	0
T24	0	308784	0	0
T25	0	119880	0	0
T30	2032	2032	0	0
T31	0	66480	0	0
T33	0	37760	0	0
T34	0	158240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717370883	574657583	0	0
T1	471681	471598	0	0
T2	1068643	603382	0	0
T3	48490	30688	0	0
T4	489568	419985	0	0
T5	150169	124794	0	0
T6	717059	637629	0	0
T7	9700	9461	0	0
T8	11587	9713	0	0
T9	2287283	1316442	0	0
T10	495701	439107	0	0
T11	0	28714	0	0
T12	0	397833	0	0
T13	0	102368	0	0
T22	0	1312	0	0
T24	0	308784	0	0
T25	0	119880	0	0
T30	2032	2032	0	0
T31	0	66480	0	0
T33	0	37760	0	0
T34	0	158240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717370883	3500155	0	0
T1	419661	832	0	0
T2	608937	7239	0	0
T3	30762	832	0	0
T4	420051	1088	0	0
T5	125337	832	0	0
T6	637705	1856	0	0
T7	9540	832	0	0
T8	9803	832	0	0
T9	2287283	20564	0	0
T10	495701	0	0	0
T11	28760	3	0	0
T12	401837	400	0	0
T13	0	8716	0	0
T22	0	105	0	0
T24	0	4983	0	0
T25	0	4566	0	0
T27	0	116	0	0
T30	4064	184	0	0
T31	70620	2839	0	0
T33	115915	11383	0	0
T34	0	4943	0	0
T40	139736	1028	0	0
T41	274091	0	0	0
T44	129766	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717370883	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717370883	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717370883	3500155	0	0
T1	419661	832	0	0
T2	608937	7239	0	0
T3	30762	832	0	0
T4	420051	1088	0	0
T5	125337	832	0	0
T6	637705	1856	0	0
T7	9540	832	0	0
T8	9803	832	0	0
T9	2287283	20564	0	0
T10	495701	0	0	0
T11	28760	3	0	0
T12	401837	400	0	0
T13	0	8716	0	0
T22	0	105	0	0
T24	0	4983	0	0
T25	0	4566	0	0
T27	0	116	0	0
T30	4064	184	0	0
T31	70620	2839	0	0
T33	115915	11383	0	0
T34	0	4943	0	0
T40	139736	1028	0	0
T41	274091	0	0	0
T44	129766	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717370883	3500155	0	0
T1	419661	832	0	0
T2	608937	7239	0	0
T3	30762	832	0	0
T4	420051	1088	0	0
T5	125337	832	0	0
T6	637705	1856	0	0
T7	9540	832	0	0
T8	9803	832	0	0
T9	2287283	20564	0	0
T10	495701	0	0	0
T11	28760	3	0	0
T12	401837	400	0	0
T13	0	8716	0	0
T22	0	105	0	0
T24	0	4983	0	0
T25	0	4566	0	0
T27	0	116	0	0
T30	4064	184	0	0
T31	70620	2839	0	0
T33	115915	11383	0	0
T34	0	4943	0	0
T40	139736	1028	0	0
T41	274091	0	0	0
T44	129766	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717370883	3500155	0	0
T1	419661	832	0	0
T2	608937	7239	0	0
T3	30762	832	0	0
T4	420051	1088	0	0
T5	125337	832	0	0
T6	637705	1856	0	0
T7	9540	832	0	0
T8	9803	832	0	0
T9	2287283	20564	0	0
T10	495701	0	0	0
T11	28760	3	0	0
T12	401837	400	0	0
T13	0	8716	0	0
T22	0	105	0	0
T24	0	4983	0	0
T25	0	4566	0	0
T27	0	116	0	0
T30	4064	184	0	0
T31	70620	2839	0	0
T33	115915	11383	0	0
T34	0	4943	0	0
T40	139736	1028	0	0
T41	274091	0	0	0
T44	129766	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	717370883	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717370883	3	0	956
T38	0	1	0	0
T50	718882	1	0	1
T51	0	1	0	0
T52	319709	0	0	1
T53	418708	0	0	1
T54	320917	0	0	1
T55	4269	0	0	1
T56	1080	0	0	1
T57	470106	0	0	1
T58	84150	0	0	1
T59	495431	0	0	1
T60	39944	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717370883	574657583	0	0
T1	471681	471598	0	0
T2	1068643	603382	0	0
T3	48490	30688	0	0
T4	489568	419985	0	0
T5	150169	124794	0	0
T6	717059	637629	0	0
T7	9700	9461	0	0
T8	11587	9713	0	0
T9	2287283	1316442	0	0
T10	495701	439107	0	0
T11	0	28714	0	0
T12	0	397833	0	0
T13	0	102368	0	0
T22	0	1312	0	0
T24	0	308784	0	0
T25	0	119880	0	0
T30	2032	2032	0	0
T31	0	66480	0	0
T33	0	37760	0	0
T34	0	158240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717370883	3500155	0	0
T1	419661	832	0	0
T2	608937	7239	0	0
T3	30762	832	0	0
T4	420051	1088	0	0
T5	125337	832	0	0
T6	637705	1856	0	0
T7	9540	832	0	0
T8	9803	832	0	0
T9	2287283	20564	0	0
T10	495701	0	0	0
T11	28760	3	0	0
T12	401837	400	0	0
T13	0	8716	0	0
T22	0	105	0	0
T24	0	4983	0	0
T25	0	4566	0	0
T27	0	116	0	0
T30	4064	184	0	0
T31	70620	2839	0	0
T33	115915	11383	0	0
T34	0	4943	0	0
T40	139736	1028	0	0
T41	274091	0	0	0
T44	129766	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T30,T31
1	0	Covered	T2,T30,T31

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T30
1	0	Unreachable
1	1	Covered	T2,T30,T31

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T30,T31
0	0	1	Unreachable
0	0	0	Covered	T2,T10,T30

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T30,T31
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T30,T31
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	141345120	26918802	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	141345120	586711	0	0
GntImpliesValid_A	141345120	586711	0	0
GrantKnown_A	141345120	26918802	0	0
IdxKnown_A	141345120	26918802	0	0
IndexIsCorrect_A	141345120	586711	0	0
LockArbDecision_A	141345120	0	0	0
NoReadyValidNoGrant_A	141345120	0	0	0
ReadyAndValidImplyGrant_A	141345120	586711	0	0
ReqAndReadyImplyGrant_A	141345120	586711	0	0
ReqImpliesValid_A	141345120	586711	0	0
ReqStaysHighUntilGranted0_M	141345120	0	0	0
RoundRobin_A	141345120	0	0	0
ValidKnown_A	141345120	26918802	0	0
gen_data_port_assertion.DataFlow_A	141345120	586711	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	26918802	0	0
T2	459706	454216	0	0
T3	17728	0	0	0
T4	69517	0	0	0
T5	24832	0	0	0
T6	79354	0	0	0
T7	160	0	0	0
T8	1784	0	0	0
T9	966359	0	0	0
T10	55212	53912	0	0
T13	0	102368	0	0
T22	0	1312	0	0
T24	0	308784	0	0
T25	0	119880	0	0
T30	2032	2032	0	0
T31	0	66480	0	0
T33	0	37760	0	0
T34	0	158240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	586711	0	0
T2	459706	4906	0	0
T3	17728	0	0	0
T4	69517	0	0	0
T5	24832	0	0	0
T6	79354	0	0	0
T7	160	0	0	0
T8	1784	0	0	0
T9	966359	0	0	0
T10	55212	0	0	0
T13	0	4289	0	0
T22	0	105	0	0
T24	0	4983	0	0
T25	0	2912	0	0
T27	0	116	0	0
T30	2032	134	0	0
T31	0	2839	0	0
T33	0	1644	0	0
T34	0	4055	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	586711	0	0
T2	459706	4906	0	0
T3	17728	0	0	0
T4	69517	0	0	0
T5	24832	0	0	0
T6	79354	0	0	0
T7	160	0	0	0
T8	1784	0	0	0
T9	966359	0	0	0
T10	55212	0	0	0
T13	0	4289	0	0
T22	0	105	0	0
T24	0	4983	0	0
T25	0	2912	0	0
T27	0	116	0	0
T30	2032	134	0	0
T31	0	2839	0	0
T33	0	1644	0	0
T34	0	4055	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	26918802	0	0
T2	459706	454216	0	0
T3	17728	0	0	0
T4	69517	0	0	0
T5	24832	0	0	0
T6	79354	0	0	0
T7	160	0	0	0
T8	1784	0	0	0
T9	966359	0	0	0
T10	55212	53912	0	0
T13	0	102368	0	0
T22	0	1312	0	0
T24	0	308784	0	0
T25	0	119880	0	0
T30	2032	2032	0	0
T31	0	66480	0	0
T33	0	37760	0	0
T34	0	158240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	26918802	0	0
T2	459706	454216	0	0
T3	17728	0	0	0
T4	69517	0	0	0
T5	24832	0	0	0
T6	79354	0	0	0
T7	160	0	0	0
T8	1784	0	0	0
T9	966359	0	0	0
T10	55212	53912	0	0
T13	0	102368	0	0
T22	0	1312	0	0
T24	0	308784	0	0
T25	0	119880	0	0
T30	2032	2032	0	0
T31	0	66480	0	0
T33	0	37760	0	0
T34	0	158240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	586711	0	0
T2	459706	4906	0	0
T3	17728	0	0	0
T4	69517	0	0	0
T5	24832	0	0	0
T6	79354	0	0	0
T7	160	0	0	0
T8	1784	0	0	0
T9	966359	0	0	0
T10	55212	0	0	0
T13	0	4289	0	0
T22	0	105	0	0
T24	0	4983	0	0
T25	0	2912	0	0
T27	0	116	0	0
T30	2032	134	0	0
T31	0	2839	0	0
T33	0	1644	0	0
T34	0	4055	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	586711	0	0
T2	459706	4906	0	0
T3	17728	0	0	0
T4	69517	0	0	0
T5	24832	0	0	0
T6	79354	0	0	0
T7	160	0	0	0
T8	1784	0	0	0
T9	966359	0	0	0
T10	55212	0	0	0
T13	0	4289	0	0
T22	0	105	0	0
T24	0	4983	0	0
T25	0	2912	0	0
T27	0	116	0	0
T30	2032	134	0	0
T31	0	2839	0	0
T33	0	1644	0	0
T34	0	4055	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	586711	0	0
T2	459706	4906	0	0
T3	17728	0	0	0
T4	69517	0	0	0
T5	24832	0	0	0
T6	79354	0	0	0
T7	160	0	0	0
T8	1784	0	0	0
T9	966359	0	0	0
T10	55212	0	0	0
T13	0	4289	0	0
T22	0	105	0	0
T24	0	4983	0	0
T25	0	2912	0	0
T27	0	116	0	0
T30	2032	134	0	0
T31	0	2839	0	0
T33	0	1644	0	0
T34	0	4055	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	586711	0	0
T2	459706	4906	0	0
T3	17728	0	0	0
T4	69517	0	0	0
T5	24832	0	0	0
T6	79354	0	0	0
T7	160	0	0	0
T8	1784	0	0	0
T9	966359	0	0	0
T10	55212	0	0	0
T13	0	4289	0	0
T22	0	105	0	0
T24	0	4983	0	0
T25	0	2912	0	0
T27	0	116	0	0
T30	2032	134	0	0
T31	0	2839	0	0
T33	0	1644	0	0
T34	0	4055	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	26918802	0	0
T2	459706	454216	0	0
T3	17728	0	0	0
T4	69517	0	0	0
T5	24832	0	0	0
T6	79354	0	0	0
T7	160	0	0	0
T8	1784	0	0	0
T9	966359	0	0	0
T10	55212	53912	0	0
T13	0	102368	0	0
T22	0	1312	0	0
T24	0	308784	0	0
T25	0	119880	0	0
T30	2032	2032	0	0
T31	0	66480	0	0
T33	0	37760	0	0
T34	0	158240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	586711	0	0
T2	459706	4906	0	0
T3	17728	0	0	0
T4	69517	0	0	0
T5	24832	0	0	0
T6	79354	0	0	0
T7	160	0	0	0
T8	1784	0	0	0
T9	966359	0	0	0
T10	55212	0	0	0
T13	0	4289	0	0
T22	0	105	0	0
T24	0	4983	0	0
T25	0	2912	0	0
T27	0	116	0	0
T30	2032	134	0	0
T31	0	2839	0	0
T33	0	1644	0	0
T34	0	4055	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T11,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T11,T12
1	0	Covered	T9,T11,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T9,T11,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T9,T11,T12
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	141345120	113144174	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	141345120	754902	0	0
GntImpliesValid_A	141345120	754902	0	0
GrantKnown_A	141345120	113144174	0	0
IdxKnown_A	141345120	113144174	0	0
IndexIsCorrect_A	141345120	754902	0	0
LockArbDecision_A	141345120	0	0	0
NoReadyValidNoGrant_A	141345120	0	0	0
ReadyAndValidImplyGrant_A	141345120	754902	0	0
ReqAndReadyImplyGrant_A	141345120	754902	0	0
ReqImpliesValid_A	141345120	754902	0	0
ReqStaysHighUntilGranted0_M	141345120	0	0	0
RoundRobin_A	141345120	0	0	0
ValidKnown_A	141345120	113144174	0	0
gen_data_port_assertion.DataFlow_A	141345120	754902	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	113144174	0	0
T1	52020	52020	0	0
T2	459706	0	0	0
T3	17728	17728	0	0
T4	69517	69517	0	0
T5	24832	24346	0	0
T6	79354	79354	0	0
T7	160	160	0	0
T8	1784	1784	0	0
T9	966359	961945	0	0
T10	55212	0	0	0
T11	0	28714	0	0
T12	0	397833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	754902	0	0
T9	966359	9158	0	0
T10	55212	0	0	0
T11	28760	3	0	0
T12	401837	400	0	0
T13	0	4427	0	0
T25	0	1654	0	0
T30	2032	0	0	0
T31	70620	0	0	0
T33	115915	9739	0	0
T34	0	888	0	0
T39	0	516	0	0
T40	139736	1028	0	0
T41	274091	3523	0	0
T44	129766	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	754902	0	0
T9	966359	9158	0	0
T10	55212	0	0	0
T11	28760	3	0	0
T12	401837	400	0	0
T13	0	4427	0	0
T25	0	1654	0	0
T30	2032	0	0	0
T31	70620	0	0	0
T33	115915	9739	0	0
T34	0	888	0	0
T39	0	516	0	0
T40	139736	1028	0	0
T41	274091	3523	0	0
T44	129766	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	113144174	0	0
T1	52020	52020	0	0
T2	459706	0	0	0
T3	17728	17728	0	0
T4	69517	69517	0	0
T5	24832	24346	0	0
T6	79354	79354	0	0
T7	160	160	0	0
T8	1784	1784	0	0
T9	966359	961945	0	0
T10	55212	0	0	0
T11	0	28714	0	0
T12	0	397833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	113144174	0	0
T1	52020	52020	0	0
T2	459706	0	0	0
T3	17728	17728	0	0
T4	69517	69517	0	0
T5	24832	24346	0	0
T6	79354	79354	0	0
T7	160	160	0	0
T8	1784	1784	0	0
T9	966359	961945	0	0
T10	55212	0	0	0
T11	0	28714	0	0
T12	0	397833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	754902	0	0
T9	966359	9158	0	0
T10	55212	0	0	0
T11	28760	3	0	0
T12	401837	400	0	0
T13	0	4427	0	0
T25	0	1654	0	0
T30	2032	0	0	0
T31	70620	0	0	0
T33	115915	9739	0	0
T34	0	888	0	0
T39	0	516	0	0
T40	139736	1028	0	0
T41	274091	3523	0	0
T44	129766	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	754902	0	0
T9	966359	9158	0	0
T10	55212	0	0	0
T11	28760	3	0	0
T12	401837	400	0	0
T13	0	4427	0	0
T25	0	1654	0	0
T30	2032	0	0	0
T31	70620	0	0	0
T33	115915	9739	0	0
T34	0	888	0	0
T39	0	516	0	0
T40	139736	1028	0	0
T41	274091	3523	0	0
T44	129766	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	754902	0	0
T9	966359	9158	0	0
T10	55212	0	0	0
T11	28760	3	0	0
T12	401837	400	0	0
T13	0	4427	0	0
T25	0	1654	0	0
T30	2032	0	0	0
T31	70620	0	0	0
T33	115915	9739	0	0
T34	0	888	0	0
T39	0	516	0	0
T40	139736	1028	0	0
T41	274091	3523	0	0
T44	129766	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	754902	0	0
T9	966359	9158	0	0
T10	55212	0	0	0
T11	28760	3	0	0
T12	401837	400	0	0
T13	0	4427	0	0
T25	0	1654	0	0
T30	2032	0	0	0
T31	70620	0	0	0
T33	115915	9739	0	0
T34	0	888	0	0
T39	0	516	0	0
T40	139736	1028	0	0
T41	274091	3523	0	0
T44	129766	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	113144174	0	0
T1	52020	52020	0	0
T2	459706	0	0	0
T3	17728	17728	0	0
T4	69517	69517	0	0
T5	24832	24346	0	0
T6	79354	79354	0	0
T7	160	160	0	0
T8	1784	1784	0	0
T9	966359	961945	0	0
T10	55212	0	0	0
T11	0	28714	0	0
T12	0	397833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141345120	754902	0	0
T9	966359	9158	0	0
T10	55212	0	0	0
T11	28760	3	0	0
T12	401837	400	0	0
T13	0	4427	0	0
T25	0	1654	0	0
T30	2032	0	0	0
T31	70620	0	0	0
T33	115915	9739	0	0
T34	0	888	0	0
T39	0	516	0	0
T40	139736	1028	0	0
T41	274091	3523	0	0
T44	129766	0	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T9,T30

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T30
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T30
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434680643	434594607	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	434680643	2158542	0	0
GntImpliesValid_A	434680643	2158542	0	0
GrantKnown_A	434680643	434594607	0	0
IdxKnown_A	434680643	434594607	0	0
IndexIsCorrect_A	434680643	2158542	0	0
LockArbDecision_A	434680643	0	0	0
NoReadyValidNoGrant_A	434680643	0	0	0
ReadyAndValidImplyGrant_A	434680643	2158542	0	0
ReqAndReadyImplyGrant_A	434680643	2158542	0	0
ReqImpliesValid_A	434680643	2158542	0	0
ReqStaysHighUntilGranted0_M	434680643	0	0	0
RoundRobin_A	434680643	3	0	956
ValidKnown_A	434680643	434594607	0	0
gen_data_port_assertion.DataFlow_A	434680643	2158542	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434680643	434594607	0	0
T1	419661	419578	0	0
T2	149231	149166	0	0
T3	13034	12960	0	0
T4	350534	350468	0	0
T5	100505	100448	0	0
T6	558351	558275	0	0
T7	9380	9301	0	0
T8	8019	7929	0	0
T9	354565	354497	0	0
T10	385277	385195	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434680643	2158542	0	0
T1	419661	832	0	0
T2	149231	2333	0	0
T3	13034	832	0	0
T4	350534	1088	0	0
T5	100505	832	0	0
T6	558351	1856	0	0
T7	9380	832	0	0
T8	8019	832	0	0
T9	354565	11406	0	0
T10	385277	0	0	0
T30	0	50	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434680643	2158542	0	0
T1	419661	832	0	0
T2	149231	2333	0	0
T3	13034	832	0	0
T4	350534	1088	0	0
T5	100505	832	0	0
T6	558351	1856	0	0
T7	9380	832	0	0
T8	8019	832	0	0
T9	354565	11406	0	0
T10	385277	0	0	0
T30	0	50	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434680643	434594607	0	0
T1	419661	419578	0	0
T2	149231	149166	0	0
T3	13034	12960	0	0
T4	350534	350468	0	0
T5	100505	100448	0	0
T6	558351	558275	0	0
T7	9380	9301	0	0
T8	8019	7929	0	0
T9	354565	354497	0	0
T10	385277	385195	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434680643	434594607	0	0
T1	419661	419578	0	0
T2	149231	149166	0	0
T3	13034	12960	0	0
T4	350534	350468	0	0
T5	100505	100448	0	0
T6	558351	558275	0	0
T7	9380	9301	0	0
T8	8019	7929	0	0
T9	354565	354497	0	0
T10	385277	385195	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434680643	2158542	0	0
T1	419661	832	0	0
T2	149231	2333	0	0
T3	13034	832	0	0
T4	350534	1088	0	0
T5	100505	832	0	0
T6	558351	1856	0	0
T7	9380	832	0	0
T8	8019	832	0	0
T9	354565	11406	0	0
T10	385277	0	0	0
T30	0	50	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434680643	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434680643	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434680643	2158542	0	0
T1	419661	832	0	0
T2	149231	2333	0	0
T3	13034	832	0	0
T4	350534	1088	0	0
T5	100505	832	0	0
T6	558351	1856	0	0
T7	9380	832	0	0
T8	8019	832	0	0
T9	354565	11406	0	0
T10	385277	0	0	0
T30	0	50	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434680643	2158542	0	0
T1	419661	832	0	0
T2	149231	2333	0	0
T3	13034	832	0	0
T4	350534	1088	0	0
T5	100505	832	0	0
T6	558351	1856	0	0
T7	9380	832	0	0
T8	8019	832	0	0
T9	354565	11406	0	0
T10	385277	0	0	0
T30	0	50	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434680643	2158542	0	0
T1	419661	832	0	0
T2	149231	2333	0	0
T3	13034	832	0	0
T4	350534	1088	0	0
T5	100505	832	0	0
T6	558351	1856	0	0
T7	9380	832	0	0
T8	8019	832	0	0
T9	354565	11406	0	0
T10	385277	0	0	0
T30	0	50	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434680643	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434680643	3	0	956
T38	0	1	0	0
T50	718882	1	0	1
T51	0	1	0	0
T52	319709	0	0	1
T53	418708	0	0	1
T54	320917	0	0	1
T55	4269	0	0	1
T56	1080	0	0	1
T57	470106	0	0	1
T58	84150	0	0	1
T59	495431	0	0	1
T60	39944	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434680643	434594607	0	0
T1	419661	419578	0	0
T2	149231	149166	0	0
T3	13034	12960	0	0
T4	350534	350468	0	0
T5	100505	100448	0	0
T6	558351	558275	0	0
T7	9380	9301	0	0
T8	8019	7929	0	0
T9	354565	354497	0	0
T10	385277	385195	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434680643	2158542	0	0
T1	419661	832	0	0
T2	149231	2333	0	0
T3	13034	832	0	0
T4	350534	1088	0	0
T5	100505	832	0	0
T6	558351	1856	0	0
T7	9380	832	0	0
T8	8019	832	0	0
T9	354565	11406	0	0
T10	385277	0	0	0
T30	0	50	0	0