Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3591978	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4201792

1

T1

3508

T2

169

T3

951

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4309395	1			T1	3569		T2	1		T3	118
values[0x0]	1740305	1			T1	1726		T2	109		T3	459
values[0x1]	1744070	1			T1	1658		T2	102		T3	436

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2548481	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5245289

1

T1

4525

T2

175

T3

965

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	31456	1			T1	35		T3	1		T7	3
valid_sources[0x01]	31711	1			T1	26		T2	1		T3	3
valid_sources[0x02]	29394	1			T1	30		T3	6		T7	2
valid_sources[0x03]	32197	1			T1	30		T2	1		T3	9
valid_sources[0x04]	32968	1			T1	28		T2	3		T3	5
valid_sources[0x05]	30766	1			T1	21		T2	1		T3	4
valid_sources[0x06]	28688	1			T1	34		T3	3		T6	2
valid_sources[0x07]	36352	1			T1	29		T2	1		T3	3
valid_sources[0x08]	70943	1			T1	43		T7	4		T9	7
valid_sources[0x09]	37241	1			T1	28		T2	1		T3	4
valid_sources[0x0a]	28144	1			T1	29		T2	1		T7	6
valid_sources[0x0b]	32464	1			T1	22		T2	3		T3	4
valid_sources[0x0c]	26775	1			T1	24		T2	2		T3	5
valid_sources[0x0d]	29056	1			T1	26		T3	4		T7	2
valid_sources[0x0e]	28168	1			T1	23		T3	1		T7	2
valid_sources[0x0f]	27470	1			T1	30		T2	1		T3	4
valid_sources[0x10]	38480	1			T1	26		T3	4		T7	4
valid_sources[0x11]	33605	1			T1	29		T3	3		T6	1
valid_sources[0x12]	29062	1			T1	25		T2	2		T3	5
valid_sources[0x13]	28421	1			T1	26		T3	8		T7	1
valid_sources[0x14]	29472	1			T1	24		T3	6		T7	5
valid_sources[0x15]	29273	1			T1	19		T2	1		T3	7
valid_sources[0x16]	30106	1			T1	24		T2	1		T3	5
valid_sources[0x17]	30463	1			T1	24		T3	2		T6	1
valid_sources[0x18]	29545	1			T1	35		T3	3		T7	8
valid_sources[0x19]	29003	1			T1	23		T2	1		T3	3
valid_sources[0x1a]	31503	1			T1	34		T2	2		T3	6
valid_sources[0x1b]	27364	1			T1	25		T3	2		T9	6
valid_sources[0x1c]	27575	1			T1	23		T3	4		T7	3
valid_sources[0x1d]	27704	1			T1	30		T2	1		T3	2
valid_sources[0x1e]	30480	1			T1	27		T2	1		T3	2
valid_sources[0x1f]	32313	1			T1	34		T2	1		T3	4
valid_sources[0x20]	28297	1			T1	32		T2	1		T3	3
valid_sources[0x21]	28683	1			T1	20		T3	1		T6	2
valid_sources[0x22]	29000	1			T1	27		T3	2		T7	2
valid_sources[0x23]	29393	1			T1	38		T2	1		T3	1
valid_sources[0x24]	31599	1			T1	29		T3	1		T7	3
valid_sources[0x25]	29062	1			T1	29		T2	3		T3	1
valid_sources[0x26]	29161	1			T1	28		T2	2		T3	2
valid_sources[0x27]	30480	1			T1	27		T2	1		T3	8
valid_sources[0x28]	27283	1			T1	43		T3	3		T7	5
valid_sources[0x29]	33006	1			T1	19		T3	4		T7	6
valid_sources[0x2a]	29703	1			T1	32		T2	3		T3	1
valid_sources[0x2b]	27539	1			T1	25		T3	6		T9	5
valid_sources[0x2c]	33131	1			T1	25		T2	1		T3	3
valid_sources[0x2d]	30627	1			T1	31		T3	5		T7	1
valid_sources[0x2e]	30597	1			T1	31		T2	1		T3	4
valid_sources[0x2f]	28534	1			T1	28		T2	1		T3	1
valid_sources[0x30]	31101	1			T1	20		T2	2		T3	12
valid_sources[0x31]	30939	1			T1	33		T2	1		T3	11
valid_sources[0x32]	31317	1			T1	26		T2	1		T3	4
valid_sources[0x33]	30707	1			T1	25		T3	7		T7	2
valid_sources[0x34]	29154	1			T1	26		T2	1		T3	3
valid_sources[0x35]	28637	1			T1	22		T7	1		T9	14
valid_sources[0x36]	30423	1			T1	26		T3	8		T7	6
valid_sources[0x37]	29568	1			T1	27		T2	1		T3	3
valid_sources[0x38]	30566	1			T1	31		T3	3		T7	2
valid_sources[0x39]	28883	1			T1	26		T2	2		T3	1
valid_sources[0x3a]	29283	1			T1	22		T2	1		T3	4
valid_sources[0x3b]	27770	1			T1	36		T2	1		T3	2
valid_sources[0x3c]	29591	1			T1	29		T3	3		T7	6
valid_sources[0x3d]	27751	1			T1	24		T3	2		T7	3
valid_sources[0x3e]	29395	1			T1	22		T3	4		T7	4
valid_sources[0x3f]	31658	1			T1	28		T3	6		T7	2
valid_sources[0x40]	31557	1			T1	21		T3	7		T7	6
valid_sources[0x41]	31516	1			T1	24		T3	7		T9	3
valid_sources[0x42]	29741	1			T1	30		T2	1		T3	1
valid_sources[0x43]	32206	1			T1	34		T3	10		T7	4
valid_sources[0x44]	30546	1			T1	29		T2	2		T3	5
valid_sources[0x45]	30352	1			T1	30		T2	2		T3	3
valid_sources[0x46]	29479	1			T1	32		T3	3		T7	3
valid_sources[0x47]	37898	1			T1	23		T2	2		T3	12
valid_sources[0x48]	32632	1			T1	25		T7	1		T9	4
valid_sources[0x49]	32717	1			T1	27		T2	2		T3	3
valid_sources[0x4a]	28252	1			T1	32		T2	2		T3	3
valid_sources[0x4b]	27561	1			T1	25		T3	5		T7	8
valid_sources[0x4c]	31761	1			T1	20		T3	4		T7	4
valid_sources[0x4d]	30178	1			T1	23		T3	7		T7	6
valid_sources[0x4e]	36606	1			T1	28		T2	1		T3	6
valid_sources[0x4f]	29575	1			T1	21		T3	5		T9	6
valid_sources[0x50]	32671	1			T1	19		T3	7		T7	2
valid_sources[0x51]	30738	1			T1	32		T2	3		T3	8
valid_sources[0x52]	30688	1			T1	33		T3	5		T7	5
valid_sources[0x53]	27983	1			T1	27		T3	1		T7	5
valid_sources[0x54]	27405	1			T1	33		T2	2		T3	5
valid_sources[0x55]	28859	1			T1	24		T2	1		T3	5
valid_sources[0x56]	27501	1			T1	38		T2	1		T3	9
valid_sources[0x57]	27729	1			T1	22		T3	6		T7	4
valid_sources[0x58]	28958	1			T1	31		T3	8		T7	4
valid_sources[0x59]	31595	1			T1	22		T7	4		T9	7
valid_sources[0x5a]	31070	1			T1	28		T2	3		T3	5
valid_sources[0x5b]	27882	1			T1	30		T2	3		T3	6
valid_sources[0x5c]	29034	1			T1	29		T2	1		T3	6
valid_sources[0x5d]	34840	1			T1	29		T2	2		T3	4
valid_sources[0x5e]	31863	1			T1	20		T3	4		T7	6
valid_sources[0x5f]	31713	1			T1	24		T2	1		T3	2
valid_sources[0x60]	29896	1			T1	34		T3	2		T7	6
valid_sources[0x61]	28854	1			T1	27		T2	2		T6	4
valid_sources[0x62]	30951	1			T1	22		T2	2		T3	3
valid_sources[0x63]	26470	1			T1	29		T3	5		T7	4
valid_sources[0x64]	30441	1			T1	28		T2	1		T3	3
valid_sources[0x65]	29277	1			T1	26		T3	6		T7	2
valid_sources[0x66]	27565	1			T1	28		T3	4		T7	6
valid_sources[0x67]	37331	1			T1	35		T3	4		T7	2
valid_sources[0x68]	30434	1			T1	30		T2	2		T3	3
valid_sources[0x69]	29925	1			T1	32		T2	1		T3	2
valid_sources[0x6a]	28923	1			T1	31		T3	2		T7	5
valid_sources[0x6b]	28458	1			T1	28		T6	2		T7	1
valid_sources[0x6c]	31224	1			T1	35		T3	3		T7	3
valid_sources[0x6d]	28353	1			T1	37		T2	3		T3	7
valid_sources[0x6e]	31566	1			T1	27		T2	1		T3	1
valid_sources[0x6f]	31924	1			T1	26		T2	2		T3	4
valid_sources[0x70]	29857	1			T1	20		T3	4		T7	1
valid_sources[0x71]	28305	1			T1	32		T3	1		T7	3
valid_sources[0x72]	31167	1			T1	33		T3	3		T7	2
valid_sources[0x73]	27820	1			T1	16		T2	1		T3	2
valid_sources[0x74]	36896	1			T1	28		T3	8		T7	8
valid_sources[0x75]	28457	1			T1	25		T2	1		T6	6
valid_sources[0x76]	27195	1			T1	22		T3	7		T6	1
valid_sources[0x77]	27023	1			T1	23		T3	4		T7	4
valid_sources[0x78]	30151	1			T1	19		T2	2		T3	5
valid_sources[0x79]	28459	1			T1	17		T3	3		T7	3
valid_sources[0x7a]	30666	1			T1	28		T3	3		T6	2
valid_sources[0x7b]	29556	1			T1	24		T3	1		T7	3
valid_sources[0x7c]	29357	1			T1	26		T2	1		T3	2
valid_sources[0x7d]	27394	1			T1	28		T3	8		T6	1
valid_sources[0x7e]	28205	1			T1	25		T3	1		T7	2
valid_sources[0x7f]	27986	1			T1	23		T3	1		T7	1
valid_sources[0x80]	28952	1			T1	33		T2	1		T3	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1048087

1

T1

898

T3

60

T4

296

values[0x0]

all_enables

biggest_size

1587345

1

T1

1331

T2

84

T3

459

values[0x1]

all_enables

biggest_size

1566360

1

T1

1279

T2

85

T3

432