Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3613937

1

T1

3445

T2

43

T3

62

full_word

4203125

1

T1

3508

T2

169

T3

951

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7816682	1			T1	6953		T2	212		T3	1013
auto[TlIntgErrCmd]	133	1			T67	6		T96	6		T97	3
auto[TlIntgErrData]	136	1			T67	6		T96	9		T97	6
auto[TlIntgErrBoth]	111	1			T67	8		T96	5		T97	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4312845

1

T1

3569

T2

1

T3

118

auto[1]

3504217

1

T1

3384

T2

211

T3

895

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3264347	1			T1	2671		T2	1		T3	58
auto[TlIntgErrNone]	partial	auto[1]	349248	1			T1	774		T2	42		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	1048334	1			T1	898		T3	60		T4	296
auto[TlIntgErrNone]	full_word	auto[1]	3154753	1			T1	2610		T2	169		T3	891
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T67	2		T96	1		T97	2
auto[TlIntgErrCmd]	partial	auto[1]	71	1			T67	4		T96	3		T97	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T256	1		T257	1		T258	2
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T96	2		T116	1		T259	2
auto[TlIntgErrData]	partial	auto[0]	58	1			T67	4		T96	5		T97	1
auto[TlIntgErrData]	partial	auto[1]	67	1			T67	1		T96	4		T97	5
auto[TlIntgErrData]	full_word	auto[0]	7	1			T67	1		T116	2		T253	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T259	1		T253	1		T260	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T67	3		T96	2		T97	1
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T67	3		T96	3		T116	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T67	1		T116	1		T259	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T67	1		T261	1		T262	1