Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	471903602	2841454	0	0
DepthKnown_A	471903602	471770939	0	0
RvalidKnown_A	471903602	471770939	0	0
WreadyKnown_A	471903602	471770939	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	2841454	0	0
T3	100658	832	0	0
T4	20597	1663	0	0
T5	870	0	0	0
T6	1360	0	0	0
T7	90303	832	0	0
T8	2349	0	0	0
T9	23418	1663	0	0
T10	669993	19146	0	0
T11	8978	1665	0	0
T12	197212	14138	0	0
T13	0	11651	0	0
T14	0	1663	0	0
T15	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	471770939	0	0
T1	217150	217056	0	0
T2	171583	171483	0	0
T3	100658	100588	0	0
T4	20597	20502	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	90303	90231	0	0
T8	2349	2299	0	0
T9	23418	23362	0	0
T10	669993	669986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	471770939	0	0
T1	217150	217056	0	0
T2	171583	171483	0	0
T3	100658	100588	0	0
T4	20597	20502	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	90303	90231	0	0
T8	2349	2299	0	0
T9	23418	23362	0	0
T10	669993	669986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	471770939	0	0
T1	217150	217056	0	0
T2	171583	171483	0	0
T3	100658	100588	0	0
T4	20597	20502	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	90303	90231	0	0
T8	2349	2299	0	0
T9	23418	23362	0	0
T10	669993	669986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	471903602	3016316	0	0
DepthKnown_A	471903602	471770939	0	0
RvalidKnown_A	471903602	471770939	0	0
WreadyKnown_A	471903602	471770939	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	3016316	0	0
T3	100658	832	0	0
T4	20597	832	0	0
T5	870	0	0	0
T6	1360	0	0	0
T7	90303	832	0	0
T8	2349	0	0	0
T9	23418	832	0	0
T10	669993	20687	0	0
T11	8978	834	0	0
T12	197212	9152	0	0
T13	0	19197	0	0
T14	0	832	0	0
T15	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	471770939	0	0
T1	217150	217056	0	0
T2	171583	171483	0	0
T3	100658	100588	0	0
T4	20597	20502	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	90303	90231	0	0
T8	2349	2299	0	0
T9	23418	23362	0	0
T10	669993	669986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	471770939	0	0
T1	217150	217056	0	0
T2	171583	171483	0	0
T3	100658	100588	0	0
T4	20597	20502	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	90303	90231	0	0
T8	2349	2299	0	0
T9	23418	23362	0	0
T10	669993	669986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	471770939	0	0
T1	217150	217056	0	0
T2	171583	171483	0	0
T3	100658	100588	0	0
T4	20597	20502	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	90303	90231	0	0
T8	2349	2299	0	0
T9	23418	23362	0	0
T10	669993	669986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	471903602	181165	0	0
DepthKnown_A	471903602	471770939	0	0
RvalidKnown_A	471903602	471770939	0	0
WreadyKnown_A	471903602	471770939	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	181165	0	0
T1	217150	696	0	0
T2	171583	0	0	0
T3	100658	0	0	0
T4	20597	0	0	0
T5	870	0	0	0
T6	1360	0	0	0
T7	90303	0	0	0
T8	2349	0	0	0
T9	23418	0	0	0
T10	669993	1054	0	0
T12	0	448	0	0
T13	0	1007	0	0
T16	0	1809	0	0
T27	0	514	0	0
T28	0	1	0	0
T29	0	621	0	0
T30	0	966	0	0
T31	0	883	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	471770939	0	0
T1	217150	217056	0	0
T2	171583	171483	0	0
T3	100658	100588	0	0
T4	20597	20502	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	90303	90231	0	0
T8	2349	2299	0	0
T9	23418	23362	0	0
T10	669993	669986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	471770939	0	0
T1	217150	217056	0	0
T2	171583	171483	0	0
T3	100658	100588	0	0
T4	20597	20502	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	90303	90231	0	0
T8	2349	2299	0	0
T9	23418	23362	0	0
T10	669993	669986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	471770939	0	0
T1	217150	217056	0	0
T2	171583	171483	0	0
T3	100658	100588	0	0
T4	20597	20502	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	90303	90231	0	0
T8	2349	2299	0	0
T9	23418	23362	0	0
T10	669993	669986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	471903602	418077	0	0
DepthKnown_A	471903602	471770939	0	0
RvalidKnown_A	471903602	471770939	0	0
WreadyKnown_A	471903602	471770939	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	418077	0	0
T1	217150	2987	0	0
T2	171583	0	0	0
T3	100658	0	0	0
T4	20597	0	0	0
T5	870	0	0	0
T6	1360	0	0	0
T7	90303	0	0	0
T8	2349	0	0	0
T9	23418	0	0	0
T10	669993	3178	0	0
T12	0	448	0	0
T13	0	4554	0	0
T16	0	1809	0	0
T27	0	2414	0	0
T28	0	1	0	0
T29	0	621	0	0
T30	0	966	0	0
T31	0	883	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	471770939	0	0
T1	217150	217056	0	0
T2	171583	171483	0	0
T3	100658	100588	0	0
T4	20597	20502	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	90303	90231	0	0
T8	2349	2299	0	0
T9	23418	23362	0	0
T10	669993	669986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	471770939	0	0
T1	217150	217056	0	0
T2	171583	171483	0	0
T3	100658	100588	0	0
T4	20597	20502	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	90303	90231	0	0
T8	2349	2299	0	0
T9	23418	23362	0	0
T10	669993	669986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	471770939	0	0
T1	217150	217056	0	0
T2	171583	171483	0	0
T3	100658	100588	0	0
T4	20597	20502	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	90303	90231	0	0
T8	2349	2299	0	0
T9	23418	23362	0	0
T10	669993	669986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	471903602	6175537	0	0
DepthKnown_A	471903602	471770939	0	0
RvalidKnown_A	471903602	471770939	0	0
WreadyKnown_A	471903602	471770939	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	6175537	0	0
T1	217150	6711	0	0
T2	171583	212	0	0
T3	100658	181	0	0
T4	20597	644	0	0
T5	870	10	0	0
T6	1360	77	0	0
T7	90303	59	0	0
T8	2349	11	0	0
T9	23418	988	0	0
T10	669993	122510	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	471770939	0	0
T1	217150	217056	0	0
T2	171583	171483	0	0
T3	100658	100588	0	0
T4	20597	20502	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	90303	90231	0	0
T8	2349	2299	0	0
T9	23418	23362	0	0
T10	669993	669986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	471770939	0	0
T1	217150	217056	0	0
T2	171583	171483	0	0
T3	100658	100588	0	0
T4	20597	20502	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	90303	90231	0	0
T8	2349	2299	0	0
T9	23418	23362	0	0
T10	669993	669986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	471770939	0	0
T1	217150	217056	0	0
T2	171583	171483	0	0
T3	100658	100588	0	0
T4	20597	20502	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	90303	90231	0	0
T8	2349	2299	0	0
T9	23418	23362	0	0
T10	669993	669986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	471903602	12764707	0	0
DepthKnown_A	471903602	471770939	0	0
RvalidKnown_A	471903602	471770939	0	0
WreadyKnown_A	471903602	471770939	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	12764707	0	0
T1	217150	27809	0	0
T2	171583	212	0	0
T3	100658	181	0	0
T4	20597	2867	0	0
T5	870	17	0	0
T6	1360	77	0	0
T7	90303	59	0	0
T8	2349	11	0	0
T9	23418	4073	0	0
T10	669993	356705	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	471770939	0	0
T1	217150	217056	0	0
T2	171583	171483	0	0
T3	100658	100588	0	0
T4	20597	20502	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	90303	90231	0	0
T8	2349	2299	0	0
T9	23418	23362	0	0
T10	669993	669986	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	471770939	0	0
T1	217150	217056	0	0
T2	171583	171483	0	0
T3	100658	100588	0	0
T4	20597	20502	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	90303	90231	0	0
T8	2349	2299	0	0
T9	23418	23362	0	0
T10	669993	669986	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471903602	471770939	0	0
T1	217150	217056	0	0
T2	171583	171483	0	0
T3	100658	100588	0	0
T4	20597	20502	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	90303	90231	0	0
T8	2349	2299	0	0
T9	23418	23362	0	0
T10	669993	669986	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0