Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T13
1	0	Covered	T1,T10,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Unreachable
1	1	Covered	T1,T10,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T12,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T12,T13
1	0	Covered	T10,T12,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Unreachable
1	1	Covered	T10,T12,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T10,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	744809405	605739210	0	0
CheckNGreaterZero_A	2865	2865	0	0
GntImpliesReady_A	744809405	3572834	0	0
GntImpliesValid_A	744809405	3572834	0	0
GrantKnown_A	744809405	605739210	0	0
IdxKnown_A	744809405	605739210	0	0
IndexIsCorrect_A	744809405	3572834	0	0
LockArbDecision_A	744809405	0	0	0
NoReadyValidNoGrant_A	744809405	0	0	0
ReadyAndValidImplyGrant_A	744809405	3572834	0	0
ReqAndReadyImplyGrant_A	744809405	3572834	0	0
ReqImpliesValid_A	744809405	3572834	0	0
ReqStaysHighUntilGranted0_M	744809405	0	0	0
RoundRobin_A	744809405	5	0	955
ValidKnown_A	744809405	605739210	0	0
gen_data_port_assertion.DataFlow_A	744809405	3572834	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744809405	605739210	0	0
T1	420076	414520	0	0
T2	199611	199323	0	0
T3	294060	197068	0	0
T4	37109	28758	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	265559	177859	0	0
T8	2781	2515	0	0
T9	43920	33314	0	0
T10	935593	881582	0	0
T11	4192	2096	0	0
T12	764328	379566	0	0
T13	683589	674837	0	0
T14	0	33116	0	0
T15	0	140936	0	0
T16	0	262672	0	0
T28	2336	2336	0	0
T29	0	224424	0	0
T30	0	106112	0	0
T31	0	49072	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2865	2865	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744809405	3572834	0	0
T1	420076	6779	0	0
T2	199611	0	0	0
T3	197359	832	0	0
T4	28853	832	0	0
T5	870	0	0	0
T6	1360	0	0	0
T7	177931	832	0	0
T8	2565	0	0	0
T9	33669	832	0	0
T10	935593	23340	0	0
T11	4192	832	0	0
T12	764328	13490	0	0
T13	683589	14835	0	0
T14	33116	0	0	0
T15	140936	0	0	0
T16	0	11825	0	0
T27	0	8719	0	0
T28	2336	133	0	0
T29	596419	5617	0	0
T30	0	5180	0	0
T31	0	8703	0	0
T40	18010	0	0	0
T44	0	1546	0	0
T48	13041	0	0	0
T49	0	5069	0	0
T50	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744809405	3572834	0	0
T1	420076	6779	0	0
T2	199611	0	0	0
T3	197359	832	0	0
T4	28853	832	0	0
T5	870	0	0	0
T6	1360	0	0	0
T7	177931	832	0	0
T8	2565	0	0	0
T9	33669	832	0	0
T10	935593	23340	0	0
T11	4192	832	0	0
T12	764328	13490	0	0
T13	683589	14835	0	0
T14	33116	0	0	0
T15	140936	0	0	0
T16	0	11825	0	0
T27	0	8719	0	0
T28	2336	133	0	0
T29	596419	5617	0	0
T30	0	5180	0	0
T31	0	8703	0	0
T40	18010	0	0	0
T44	0	1546	0	0
T48	13041	0	0	0
T49	0	5069	0	0
T50	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744809405	605739210	0	0
T1	420076	414520	0	0
T2	199611	199323	0	0
T3	294060	197068	0	0
T4	37109	28758	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	265559	177859	0	0
T8	2781	2515	0	0
T9	43920	33314	0	0
T10	935593	881582	0	0
T11	4192	2096	0	0
T12	764328	379566	0	0
T13	683589	674837	0	0
T14	0	33116	0	0
T15	0	140936	0	0
T16	0	262672	0	0
T28	2336	2336	0	0
T29	0	224424	0	0
T30	0	106112	0	0
T31	0	49072	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744809405	605739210	0	0
T1	420076	414520	0	0
T2	199611	199323	0	0
T3	294060	197068	0	0
T4	37109	28758	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	265559	177859	0	0
T8	2781	2515	0	0
T9	43920	33314	0	0
T10	935593	881582	0	0
T11	4192	2096	0	0
T12	764328	379566	0	0
T13	683589	674837	0	0
T14	0	33116	0	0
T15	0	140936	0	0
T16	0	262672	0	0
T28	2336	2336	0	0
T29	0	224424	0	0
T30	0	106112	0	0
T31	0	49072	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744809405	3572834	0	0
T1	420076	6779	0	0
T2	199611	0	0	0
T3	197359	832	0	0
T4	28853	832	0	0
T5	870	0	0	0
T6	1360	0	0	0
T7	177931	832	0	0
T8	2565	0	0	0
T9	33669	832	0	0
T10	935593	23340	0	0
T11	4192	832	0	0
T12	764328	13490	0	0
T13	683589	14835	0	0
T14	33116	0	0	0
T15	140936	0	0	0
T16	0	11825	0	0
T27	0	8719	0	0
T28	2336	133	0	0
T29	596419	5617	0	0
T30	0	5180	0	0
T31	0	8703	0	0
T40	18010	0	0	0
T44	0	1546	0	0
T48	13041	0	0	0
T49	0	5069	0	0
T50	0	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744809405	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744809405	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744809405	3572834	0	0
T1	420076	6779	0	0
T2	199611	0	0	0
T3	197359	832	0	0
T4	28853	832	0	0
T5	870	0	0	0
T6	1360	0	0	0
T7	177931	832	0	0
T8	2565	0	0	0
T9	33669	832	0	0
T10	935593	23340	0	0
T11	4192	832	0	0
T12	764328	13490	0	0
T13	683589	14835	0	0
T14	33116	0	0	0
T15	140936	0	0	0
T16	0	11825	0	0
T27	0	8719	0	0
T28	2336	133	0	0
T29	596419	5617	0	0
T30	0	5180	0	0
T31	0	8703	0	0
T40	18010	0	0	0
T44	0	1546	0	0
T48	13041	0	0	0
T49	0	5069	0	0
T50	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744809405	3572834	0	0
T1	420076	6779	0	0
T2	199611	0	0	0
T3	197359	832	0	0
T4	28853	832	0	0
T5	870	0	0	0
T6	1360	0	0	0
T7	177931	832	0	0
T8	2565	0	0	0
T9	33669	832	0	0
T10	935593	23340	0	0
T11	4192	832	0	0
T12	764328	13490	0	0
T13	683589	14835	0	0
T14	33116	0	0	0
T15	140936	0	0	0
T16	0	11825	0	0
T27	0	8719	0	0
T28	2336	133	0	0
T29	596419	5617	0	0
T30	0	5180	0	0
T31	0	8703	0	0
T40	18010	0	0	0
T44	0	1546	0	0
T48	13041	0	0	0
T49	0	5069	0	0
T50	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744809405	3572834	0	0
T1	420076	6779	0	0
T2	199611	0	0	0
T3	197359	832	0	0
T4	28853	832	0	0
T5	870	0	0	0
T6	1360	0	0	0
T7	177931	832	0	0
T8	2565	0	0	0
T9	33669	832	0	0
T10	935593	23340	0	0
T11	4192	832	0	0
T12	764328	13490	0	0
T13	683589	14835	0	0
T14	33116	0	0	0
T15	140936	0	0	0
T16	0	11825	0	0
T27	0	8719	0	0
T28	2336	133	0	0
T29	596419	5617	0	0
T30	0	5180	0	0
T31	0	8703	0	0
T40	18010	0	0	0
T44	0	1546	0	0
T48	13041	0	0	0
T49	0	5069	0	0
T50	0	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	744809405	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744809405	5	0	955
T51	300615	1	0	1
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	210094	0	0	1
T57	1692	0	0	1
T58	32606	0	0	1
T59	365685	0	0	1
T60	662973	0	0	1
T61	143333	0	0	1
T62	4125	0	0	1
T63	1005	0	0	1
T64	27012	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744809405	605739210	0	0
T1	420076	414520	0	0
T2	199611	199323	0	0
T3	294060	197068	0	0
T4	37109	28758	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	265559	177859	0	0
T8	2781	2515	0	0
T9	43920	33314	0	0
T10	935593	881582	0	0
T11	4192	2096	0	0
T12	764328	379566	0	0
T13	683589	674837	0	0
T14	0	33116	0	0
T15	0	140936	0	0
T16	0	262672	0	0
T28	2336	2336	0	0
T29	0	224424	0	0
T30	0	106112	0	0
T31	0	49072	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744809405	3572834	0	0
T1	420076	6779	0	0
T2	199611	0	0	0
T3	197359	832	0	0
T4	28853	832	0	0
T5	870	0	0	0
T6	1360	0	0	0
T7	177931	832	0	0
T8	2565	0	0	0
T9	33669	832	0	0
T10	935593	23340	0	0
T11	4192	832	0	0
T12	764328	13490	0	0
T13	683589	14835	0	0
T14	33116	0	0	0
T15	140936	0	0	0
T16	0	11825	0	0
T27	0	8719	0	0
T28	2336	133	0	0
T29	596419	5617	0	0
T30	0	5180	0	0
T31	0	8703	0	0
T40	18010	0	0	0
T44	0	1546	0	0
T48	13041	0	0	0
T49	0	5069	0	0
T50	0	4	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T13
1	0	Covered	T1,T10,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Unreachable
1	1	Covered	T1,T10,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T10,T13
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T8

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	137637432	25822644	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	137637432	641247	0	0
GntImpliesValid_A	137637432	641247	0	0
GrantKnown_A	137637432	25822644	0	0
IdxKnown_A	137637432	25822644	0	0
IndexIsCorrect_A	137637432	641247	0	0
LockArbDecision_A	137637432	0	0	0
NoReadyValidNoGrant_A	137637432	0	0	0
ReadyAndValidImplyGrant_A	137637432	641247	0	0
ReqAndReadyImplyGrant_A	137637432	641247	0	0
ReqImpliesValid_A	137637432	641247	0	0
ReqStaysHighUntilGranted0_M	137637432	0	0	0
RoundRobin_A	137637432	0	0	0
ValidKnown_A	137637432	25822644	0	0
gen_data_port_assertion.DataFlow_A	137637432	641247	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	25822644	0	0
T1	202926	197464	0	0
T2	28028	27840	0	0
T3	96701	0	0	0
T4	8256	0	0	0
T7	87628	0	0	0
T8	216	216	0	0
T9	10251	0	0	0
T10	132800	88664	0	0
T11	2096	0	0	0
T12	382164	0	0	0
T13	0	99272	0	0
T16	0	262672	0	0
T28	0	2336	0	0
T29	0	224424	0	0
T30	0	106112	0	0
T31	0	49072	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	641247	0	0
T1	202926	4466	0	0
T2	28028	0	0	0
T3	96701	0	0	0
T4	8256	0	0	0
T7	87628	0	0	0
T8	216	0	0	0
T9	10251	0	0	0
T10	132800	3521	0	0
T11	2096	0	0	0
T12	382164	0	0	0
T13	0	3997	0	0
T16	0	7912	0	0
T28	0	70	0	0
T29	0	2809	0	0
T30	0	4686	0	0
T31	0	2013	0	0
T44	0	498	0	0
T49	0	5069	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	641247	0	0
T1	202926	4466	0	0
T2	28028	0	0	0
T3	96701	0	0	0
T4	8256	0	0	0
T7	87628	0	0	0
T8	216	0	0	0
T9	10251	0	0	0
T10	132800	3521	0	0
T11	2096	0	0	0
T12	382164	0	0	0
T13	0	3997	0	0
T16	0	7912	0	0
T28	0	70	0	0
T29	0	2809	0	0
T30	0	4686	0	0
T31	0	2013	0	0
T44	0	498	0	0
T49	0	5069	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	25822644	0	0
T1	202926	197464	0	0
T2	28028	27840	0	0
T3	96701	0	0	0
T4	8256	0	0	0
T7	87628	0	0	0
T8	216	216	0	0
T9	10251	0	0	0
T10	132800	88664	0	0
T11	2096	0	0	0
T12	382164	0	0	0
T13	0	99272	0	0
T16	0	262672	0	0
T28	0	2336	0	0
T29	0	224424	0	0
T30	0	106112	0	0
T31	0	49072	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	25822644	0	0
T1	202926	197464	0	0
T2	28028	27840	0	0
T3	96701	0	0	0
T4	8256	0	0	0
T7	87628	0	0	0
T8	216	216	0	0
T9	10251	0	0	0
T10	132800	88664	0	0
T11	2096	0	0	0
T12	382164	0	0	0
T13	0	99272	0	0
T16	0	262672	0	0
T28	0	2336	0	0
T29	0	224424	0	0
T30	0	106112	0	0
T31	0	49072	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	641247	0	0
T1	202926	4466	0	0
T2	28028	0	0	0
T3	96701	0	0	0
T4	8256	0	0	0
T7	87628	0	0	0
T8	216	0	0	0
T9	10251	0	0	0
T10	132800	3521	0	0
T11	2096	0	0	0
T12	382164	0	0	0
T13	0	3997	0	0
T16	0	7912	0	0
T28	0	70	0	0
T29	0	2809	0	0
T30	0	4686	0	0
T31	0	2013	0	0
T44	0	498	0	0
T49	0	5069	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	641247	0	0
T1	202926	4466	0	0
T2	28028	0	0	0
T3	96701	0	0	0
T4	8256	0	0	0
T7	87628	0	0	0
T8	216	0	0	0
T9	10251	0	0	0
T10	132800	3521	0	0
T11	2096	0	0	0
T12	382164	0	0	0
T13	0	3997	0	0
T16	0	7912	0	0
T28	0	70	0	0
T29	0	2809	0	0
T30	0	4686	0	0
T31	0	2013	0	0
T44	0	498	0	0
T49	0	5069	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	641247	0	0
T1	202926	4466	0	0
T2	28028	0	0	0
T3	96701	0	0	0
T4	8256	0	0	0
T7	87628	0	0	0
T8	216	0	0	0
T9	10251	0	0	0
T10	132800	3521	0	0
T11	2096	0	0	0
T12	382164	0	0	0
T13	0	3997	0	0
T16	0	7912	0	0
T28	0	70	0	0
T29	0	2809	0	0
T30	0	4686	0	0
T31	0	2013	0	0
T44	0	498	0	0
T49	0	5069	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	641247	0	0
T1	202926	4466	0	0
T2	28028	0	0	0
T3	96701	0	0	0
T4	8256	0	0	0
T7	87628	0	0	0
T8	216	0	0	0
T9	10251	0	0	0
T10	132800	3521	0	0
T11	2096	0	0	0
T12	382164	0	0	0
T13	0	3997	0	0
T16	0	7912	0	0
T28	0	70	0	0
T29	0	2809	0	0
T30	0	4686	0	0
T31	0	2013	0	0
T44	0	498	0	0
T49	0	5069	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	25822644	0	0
T1	202926	197464	0	0
T2	28028	27840	0	0
T3	96701	0	0	0
T4	8256	0	0	0
T7	87628	0	0	0
T8	216	216	0	0
T9	10251	0	0	0
T10	132800	88664	0	0
T11	2096	0	0	0
T12	382164	0	0	0
T13	0	99272	0	0
T16	0	262672	0	0
T28	0	2336	0	0
T29	0	224424	0	0
T30	0	106112	0	0
T31	0	49072	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	641247	0	0
T1	202926	4466	0	0
T2	28028	0	0	0
T3	96701	0	0	0
T4	8256	0	0	0
T7	87628	0	0	0
T8	216	0	0	0
T9	10251	0	0	0
T10	132800	3521	0	0
T11	2096	0	0	0
T12	382164	0	0	0
T13	0	3997	0	0
T16	0	7912	0	0
T28	0	70	0	0
T29	0	2809	0	0
T30	0	4686	0	0
T31	0	2013	0	0
T44	0	498	0	0
T49	0	5069	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T12,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T12,T13
1	0	Covered	T10,T12,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Unreachable
1	1	Covered	T10,T12,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T10,T12,T13
0	0	1	Unreachable
0	0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	137637432	110471038	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	137637432	711242	0	0
GntImpliesValid_A	137637432	711242	0	0
GrantKnown_A	137637432	110471038	0	0
IdxKnown_A	137637432	110471038	0	0
IndexIsCorrect_A	137637432	711242	0	0
LockArbDecision_A	137637432	0	0	0
NoReadyValidNoGrant_A	137637432	0	0	0
ReadyAndValidImplyGrant_A	137637432	711242	0	0
ReqAndReadyImplyGrant_A	137637432	711242	0	0
ReqImpliesValid_A	137637432	711242	0	0
ReqStaysHighUntilGranted0_M	137637432	0	0	0
RoundRobin_A	137637432	0	0	0
ValidKnown_A	137637432	110471038	0	0
gen_data_port_assertion.DataFlow_A	137637432	711242	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	110471038	0	0
T3	96701	96480	0	0
T4	8256	8256	0	0
T7	87628	87628	0	0
T8	216	0	0	0
T9	10251	9952	0	0
T10	132800	122932	0	0
T11	2096	2096	0	0
T12	382164	379566	0	0
T13	683589	575565	0	0
T14	0	33116	0	0
T15	0	140936	0	0
T28	2336	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	711242	0	0
T10	132800	6131	0	0
T11	2096	0	0	0
T12	382164	3858	0	0
T13	683589	1299	0	0
T14	33116	0	0	0
T15	140936	0	0	0
T16	0	3913	0	0
T27	0	8719	0	0
T28	2336	0	0	0
T29	596419	2808	0	0
T30	0	494	0	0
T31	0	6690	0	0
T40	18010	0	0	0
T44	0	1048	0	0
T48	13041	0	0	0
T50	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	711242	0	0
T10	132800	6131	0	0
T11	2096	0	0	0
T12	382164	3858	0	0
T13	683589	1299	0	0
T14	33116	0	0	0
T15	140936	0	0	0
T16	0	3913	0	0
T27	0	8719	0	0
T28	2336	0	0	0
T29	596419	2808	0	0
T30	0	494	0	0
T31	0	6690	0	0
T40	18010	0	0	0
T44	0	1048	0	0
T48	13041	0	0	0
T50	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	110471038	0	0
T3	96701	96480	0	0
T4	8256	8256	0	0
T7	87628	87628	0	0
T8	216	0	0	0
T9	10251	9952	0	0
T10	132800	122932	0	0
T11	2096	2096	0	0
T12	382164	379566	0	0
T13	683589	575565	0	0
T14	0	33116	0	0
T15	0	140936	0	0
T28	2336	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	110471038	0	0
T3	96701	96480	0	0
T4	8256	8256	0	0
T7	87628	87628	0	0
T8	216	0	0	0
T9	10251	9952	0	0
T10	132800	122932	0	0
T11	2096	2096	0	0
T12	382164	379566	0	0
T13	683589	575565	0	0
T14	0	33116	0	0
T15	0	140936	0	0
T28	2336	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	711242	0	0
T10	132800	6131	0	0
T11	2096	0	0	0
T12	382164	3858	0	0
T13	683589	1299	0	0
T14	33116	0	0	0
T15	140936	0	0	0
T16	0	3913	0	0
T27	0	8719	0	0
T28	2336	0	0	0
T29	596419	2808	0	0
T30	0	494	0	0
T31	0	6690	0	0
T40	18010	0	0	0
T44	0	1048	0	0
T48	13041	0	0	0
T50	0	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	711242	0	0
T10	132800	6131	0	0
T11	2096	0	0	0
T12	382164	3858	0	0
T13	683589	1299	0	0
T14	33116	0	0	0
T15	140936	0	0	0
T16	0	3913	0	0
T27	0	8719	0	0
T28	2336	0	0	0
T29	596419	2808	0	0
T30	0	494	0	0
T31	0	6690	0	0
T40	18010	0	0	0
T44	0	1048	0	0
T48	13041	0	0	0
T50	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	711242	0	0
T10	132800	6131	0	0
T11	2096	0	0	0
T12	382164	3858	0	0
T13	683589	1299	0	0
T14	33116	0	0	0
T15	140936	0	0	0
T16	0	3913	0	0
T27	0	8719	0	0
T28	2336	0	0	0
T29	596419	2808	0	0
T30	0	494	0	0
T31	0	6690	0	0
T40	18010	0	0	0
T44	0	1048	0	0
T48	13041	0	0	0
T50	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	711242	0	0
T10	132800	6131	0	0
T11	2096	0	0	0
T12	382164	3858	0	0
T13	683589	1299	0	0
T14	33116	0	0	0
T15	140936	0	0	0
T16	0	3913	0	0
T27	0	8719	0	0
T28	2336	0	0	0
T29	596419	2808	0	0
T30	0	494	0	0
T31	0	6690	0	0
T40	18010	0	0	0
T44	0	1048	0	0
T48	13041	0	0	0
T50	0	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	110471038	0	0
T3	96701	96480	0	0
T4	8256	8256	0	0
T7	87628	87628	0	0
T8	216	0	0	0
T9	10251	9952	0	0
T10	132800	122932	0	0
T11	2096	2096	0	0
T12	382164	379566	0	0
T13	683589	575565	0	0
T14	0	33116	0	0
T15	0	140936	0	0
T28	2336	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137637432	711242	0	0
T10	132800	6131	0	0
T11	2096	0	0	0
T12	382164	3858	0	0
T13	683589	1299	0	0
T14	33116	0	0	0
T15	140936	0	0	0
T16	0	3913	0	0
T27	0	8719	0	0
T28	2336	0	0	0
T29	596419	2808	0	0
T30	0	494	0	0
T31	0	6690	0	0
T40	18010	0	0	0
T44	0	1048	0	0
T48	13041	0	0	0
T50	0	4	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T10,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	469534541	469445528	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	469534541	2220345	0	0
GntImpliesValid_A	469534541	2220345	0	0
GrantKnown_A	469534541	469445528	0	0
IdxKnown_A	469534541	469445528	0	0
IndexIsCorrect_A	469534541	2220345	0	0
LockArbDecision_A	469534541	0	0	0
NoReadyValidNoGrant_A	469534541	0	0	0
ReadyAndValidImplyGrant_A	469534541	2220345	0	0
ReqAndReadyImplyGrant_A	469534541	2220345	0	0
ReqImpliesValid_A	469534541	2220345	0	0
ReqStaysHighUntilGranted0_M	469534541	0	0	0
RoundRobin_A	469534541	5	0	955
ValidKnown_A	469534541	469445528	0	0
gen_data_port_assertion.DataFlow_A	469534541	2220345	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469534541	469445528	0	0
T1	217150	217056	0	0
T2	171583	171483	0	0
T3	100658	100588	0	0
T4	20597	20502	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	90303	90231	0	0
T8	2349	2299	0	0
T9	23418	23362	0	0
T10	669993	669986	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469534541	2220345	0	0
T1	217150	2313	0	0
T2	171583	0	0	0
T3	100658	832	0	0
T4	20597	832	0	0
T5	870	0	0	0
T6	1360	0	0	0
T7	90303	832	0	0
T8	2349	0	0	0
T9	23418	832	0	0
T10	669993	13688	0	0
T11	0	832	0	0
T12	0	9632	0	0
T13	0	9539	0	0
T28	0	63	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469534541	2220345	0	0
T1	217150	2313	0	0
T2	171583	0	0	0
T3	100658	832	0	0
T4	20597	832	0	0
T5	870	0	0	0
T6	1360	0	0	0
T7	90303	832	0	0
T8	2349	0	0	0
T9	23418	832	0	0
T10	669993	13688	0	0
T11	0	832	0	0
T12	0	9632	0	0
T13	0	9539	0	0
T28	0	63	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469534541	469445528	0	0
T1	217150	217056	0	0
T2	171583	171483	0	0
T3	100658	100588	0	0
T4	20597	20502	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	90303	90231	0	0
T8	2349	2299	0	0
T9	23418	23362	0	0
T10	669993	669986	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469534541	469445528	0	0
T1	217150	217056	0	0
T2	171583	171483	0	0
T3	100658	100588	0	0
T4	20597	20502	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	90303	90231	0	0
T8	2349	2299	0	0
T9	23418	23362	0	0
T10	669993	669986	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469534541	2220345	0	0
T1	217150	2313	0	0
T2	171583	0	0	0
T3	100658	832	0	0
T4	20597	832	0	0
T5	870	0	0	0
T6	1360	0	0	0
T7	90303	832	0	0
T8	2349	0	0	0
T9	23418	832	0	0
T10	669993	13688	0	0
T11	0	832	0	0
T12	0	9632	0	0
T13	0	9539	0	0
T28	0	63	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469534541	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469534541	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469534541	2220345	0	0
T1	217150	2313	0	0
T2	171583	0	0	0
T3	100658	832	0	0
T4	20597	832	0	0
T5	870	0	0	0
T6	1360	0	0	0
T7	90303	832	0	0
T8	2349	0	0	0
T9	23418	832	0	0
T10	669993	13688	0	0
T11	0	832	0	0
T12	0	9632	0	0
T13	0	9539	0	0
T28	0	63	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469534541	2220345	0	0
T1	217150	2313	0	0
T2	171583	0	0	0
T3	100658	832	0	0
T4	20597	832	0	0
T5	870	0	0	0
T6	1360	0	0	0
T7	90303	832	0	0
T8	2349	0	0	0
T9	23418	832	0	0
T10	669993	13688	0	0
T11	0	832	0	0
T12	0	9632	0	0
T13	0	9539	0	0
T28	0	63	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469534541	2220345	0	0
T1	217150	2313	0	0
T2	171583	0	0	0
T3	100658	832	0	0
T4	20597	832	0	0
T5	870	0	0	0
T6	1360	0	0	0
T7	90303	832	0	0
T8	2349	0	0	0
T9	23418	832	0	0
T10	669993	13688	0	0
T11	0	832	0	0
T12	0	9632	0	0
T13	0	9539	0	0
T28	0	63	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	469534541	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469534541	5	0	955
T51	300615	1	0	1
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	210094	0	0	1
T57	1692	0	0	1
T58	32606	0	0	1
T59	365685	0	0	1
T60	662973	0	0	1
T61	143333	0	0	1
T62	4125	0	0	1
T63	1005	0	0	1
T64	27012	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469534541	469445528	0	0
T1	217150	217056	0	0
T2	171583	171483	0	0
T3	100658	100588	0	0
T4	20597	20502	0	0
T5	870	786	0	0
T6	1360	1274	0	0
T7	90303	90231	0	0
T8	2349	2299	0	0
T9	23418	23362	0	0
T10	669993	669986	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469534541	2220345	0	0
T1	217150	2313	0	0
T2	171583	0	0	0
T3	100658	832	0	0
T4	20597	832	0	0
T5	870	0	0	0
T6	1360	0	0	0
T7	90303	832	0	0
T8	2349	0	0	0
T9	23418	832	0	0
T10	669993	13688	0	0
T11	0	832	0	0
T12	0	9632	0	0
T13	0	9539	0	0
T28	0	63	0	0