Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
3862 |
0 |
0 |
T65 |
4021 |
14 |
0 |
0 |
T66 |
5346 |
6 |
0 |
0 |
T67 |
19485 |
3 |
0 |
0 |
T95 |
3688 |
155 |
0 |
0 |
T96 |
66732 |
5 |
0 |
0 |
T97 |
9977 |
3 |
0 |
0 |
T98 |
3412 |
149 |
0 |
0 |
T110 |
5825 |
5 |
0 |
0 |
T114 |
4791 |
2 |
0 |
0 |
T115 |
10643 |
7 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
2457 |
0 |
0 |
T96 |
66732 |
91 |
0 |
0 |
T114 |
4791 |
10 |
0 |
0 |
T115 |
10643 |
8 |
0 |
0 |
T116 |
100598 |
128 |
0 |
0 |
T120 |
73217 |
427 |
0 |
0 |
T121 |
6403 |
11 |
0 |
0 |
T122 |
7539 |
5 |
0 |
0 |
T155 |
7794 |
11 |
0 |
0 |
T156 |
35297 |
17 |
0 |
0 |
T157 |
6960 |
6 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
2416 |
0 |
0 |
T96 |
66732 |
92 |
0 |
0 |
T114 |
4791 |
12 |
0 |
0 |
T115 |
10643 |
6 |
0 |
0 |
T116 |
100598 |
126 |
0 |
0 |
T120 |
73217 |
461 |
0 |
0 |
T121 |
6403 |
9 |
0 |
0 |
T122 |
7539 |
5 |
0 |
0 |
T155 |
7794 |
13 |
0 |
0 |
T156 |
35297 |
28 |
0 |
0 |
T158 |
6162 |
1 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
2939 |
0 |
0 |
T96 |
66732 |
133 |
0 |
0 |
T103 |
16222 |
5 |
0 |
0 |
T114 |
4791 |
14 |
0 |
0 |
T115 |
10643 |
11 |
0 |
0 |
T116 |
100598 |
180 |
0 |
0 |
T120 |
73217 |
448 |
0 |
0 |
T121 |
6403 |
23 |
0 |
0 |
T122 |
7539 |
19 |
0 |
0 |
T155 |
7794 |
24 |
0 |
0 |
T158 |
6162 |
8 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
8675 |
0 |
0 |
T96 |
66732 |
1163 |
0 |
0 |
T114 |
4791 |
3 |
0 |
0 |
T115 |
10643 |
116 |
0 |
0 |
T116 |
100598 |
1886 |
0 |
0 |
T120 |
73217 |
518 |
0 |
0 |
T121 |
6403 |
139 |
0 |
0 |
T122 |
7539 |
114 |
0 |
0 |
T155 |
7794 |
11 |
0 |
0 |
T156 |
35297 |
911 |
0 |
0 |
T158 |
6162 |
105 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
7005 |
0 |
0 |
T96 |
66732 |
532 |
0 |
0 |
T99 |
17458 |
4 |
0 |
0 |
T114 |
4791 |
11 |
0 |
0 |
T115 |
10643 |
145 |
0 |
0 |
T116 |
100598 |
1175 |
0 |
0 |
T120 |
73217 |
470 |
0 |
0 |
T121 |
6403 |
98 |
0 |
0 |
T122 |
7539 |
115 |
0 |
0 |
T155 |
7794 |
119 |
0 |
0 |
T158 |
6162 |
6 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
9596 |
0 |
0 |
T96 |
66732 |
1538 |
0 |
0 |
T114 |
4791 |
8 |
0 |
0 |
T115 |
10643 |
133 |
0 |
0 |
T116 |
100598 |
2143 |
0 |
0 |
T120 |
73217 |
472 |
0 |
0 |
T121 |
6403 |
234 |
0 |
0 |
T122 |
7539 |
90 |
0 |
0 |
T155 |
7794 |
219 |
0 |
0 |
T156 |
35297 |
543 |
0 |
0 |
T158 |
6162 |
12 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
7802 |
0 |
0 |
T96 |
66732 |
882 |
0 |
0 |
T103 |
16222 |
3 |
0 |
0 |
T114 |
4791 |
122 |
0 |
0 |
T115 |
10643 |
209 |
0 |
0 |
T116 |
100598 |
1327 |
0 |
0 |
T120 |
73217 |
423 |
0 |
0 |
T122 |
7539 |
111 |
0 |
0 |
T155 |
7794 |
116 |
0 |
0 |
T156 |
35297 |
621 |
0 |
0 |
T158 |
6162 |
140 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
8980 |
0 |
0 |
T96 |
66732 |
1449 |
0 |
0 |
T114 |
4791 |
11 |
0 |
0 |
T115 |
10643 |
208 |
0 |
0 |
T116 |
100598 |
1911 |
0 |
0 |
T120 |
73217 |
470 |
0 |
0 |
T121 |
6403 |
112 |
0 |
0 |
T122 |
7539 |
237 |
0 |
0 |
T155 |
7794 |
3 |
0 |
0 |
T156 |
35297 |
627 |
0 |
0 |
T158 |
6162 |
102 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
9035 |
0 |
0 |
T96 |
66732 |
1987 |
0 |
0 |
T114 |
4791 |
11 |
0 |
0 |
T115 |
10643 |
225 |
0 |
0 |
T116 |
100598 |
1778 |
0 |
0 |
T120 |
73217 |
422 |
0 |
0 |
T121 |
6403 |
127 |
0 |
0 |
T122 |
7539 |
9 |
0 |
0 |
T155 |
7794 |
136 |
0 |
0 |
T156 |
35297 |
362 |
0 |
0 |
T158 |
6162 |
112 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
7824 |
0 |
0 |
T96 |
66732 |
819 |
0 |
0 |
T114 |
4791 |
143 |
0 |
0 |
T115 |
10643 |
224 |
0 |
0 |
T116 |
100598 |
1888 |
0 |
0 |
T120 |
73217 |
472 |
0 |
0 |
T121 |
6403 |
5 |
0 |
0 |
T122 |
7539 |
127 |
0 |
0 |
T155 |
7794 |
121 |
0 |
0 |
T156 |
35297 |
459 |
0 |
0 |
T158 |
6162 |
4 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
8476 |
0 |
0 |
T96 |
66732 |
667 |
0 |
0 |
T114 |
4791 |
16 |
0 |
0 |
T115 |
10643 |
5 |
0 |
0 |
T116 |
100598 |
1740 |
0 |
0 |
T120 |
73217 |
500 |
0 |
0 |
T121 |
6403 |
243 |
0 |
0 |
T122 |
7539 |
97 |
0 |
0 |
T155 |
7794 |
139 |
0 |
0 |
T156 |
35297 |
742 |
0 |
0 |
T158 |
6162 |
131 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
4876 |
0 |
0 |
T96 |
66732 |
555 |
0 |
0 |
T114 |
4791 |
8 |
0 |
0 |
T115 |
10643 |
61 |
0 |
0 |
T116 |
100598 |
627 |
0 |
0 |
T120 |
73217 |
421 |
0 |
0 |
T121 |
6403 |
73 |
0 |
0 |
T122 |
7539 |
40 |
0 |
0 |
T155 |
7794 |
61 |
0 |
0 |
T156 |
35297 |
281 |
0 |
0 |
T158 |
6162 |
66 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
5049 |
0 |
0 |
T96 |
66732 |
505 |
0 |
0 |
T114 |
4791 |
45 |
0 |
0 |
T115 |
10643 |
52 |
0 |
0 |
T116 |
100598 |
835 |
0 |
0 |
T120 |
73217 |
393 |
0 |
0 |
T121 |
6403 |
78 |
0 |
0 |
T122 |
7539 |
61 |
0 |
0 |
T155 |
7794 |
116 |
0 |
0 |
T156 |
35297 |
157 |
0 |
0 |
T158 |
6162 |
55 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
4492 |
0 |
0 |
T96 |
66732 |
586 |
0 |
0 |
T114 |
4791 |
1 |
0 |
0 |
T115 |
10643 |
65 |
0 |
0 |
T116 |
100598 |
691 |
0 |
0 |
T120 |
73217 |
470 |
0 |
0 |
T121 |
6403 |
16 |
0 |
0 |
T122 |
7539 |
44 |
0 |
0 |
T155 |
7794 |
12 |
0 |
0 |
T156 |
35297 |
228 |
0 |
0 |
T158 |
6162 |
77 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
4918 |
0 |
0 |
T96 |
66732 |
677 |
0 |
0 |
T114 |
4791 |
50 |
0 |
0 |
T115 |
10643 |
47 |
0 |
0 |
T116 |
100598 |
518 |
0 |
0 |
T120 |
73217 |
490 |
0 |
0 |
T121 |
6403 |
7 |
0 |
0 |
T122 |
7539 |
40 |
0 |
0 |
T155 |
7794 |
2 |
0 |
0 |
T156 |
35297 |
290 |
0 |
0 |
T158 |
6162 |
8 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
4965 |
0 |
0 |
T96 |
66732 |
667 |
0 |
0 |
T114 |
4791 |
51 |
0 |
0 |
T115 |
10643 |
7 |
0 |
0 |
T116 |
100598 |
659 |
0 |
0 |
T120 |
73217 |
501 |
0 |
0 |
T121 |
6403 |
4 |
0 |
0 |
T122 |
7539 |
6 |
0 |
0 |
T155 |
7794 |
49 |
0 |
0 |
T156 |
35297 |
162 |
0 |
0 |
T158 |
6162 |
3 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
4983 |
0 |
0 |
T96 |
66732 |
587 |
0 |
0 |
T114 |
4791 |
61 |
0 |
0 |
T115 |
10643 |
70 |
0 |
0 |
T116 |
100598 |
815 |
0 |
0 |
T120 |
73217 |
487 |
0 |
0 |
T121 |
6403 |
4 |
0 |
0 |
T122 |
7539 |
49 |
0 |
0 |
T155 |
7794 |
7 |
0 |
0 |
T156 |
35297 |
362 |
0 |
0 |
T158 |
6162 |
6 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
4844 |
0 |
0 |
T96 |
66732 |
648 |
0 |
0 |
T114 |
4791 |
4 |
0 |
0 |
T115 |
10643 |
44 |
0 |
0 |
T116 |
100598 |
689 |
0 |
0 |
T120 |
73217 |
439 |
0 |
0 |
T121 |
6403 |
75 |
0 |
0 |
T122 |
7539 |
68 |
0 |
0 |
T155 |
7794 |
71 |
0 |
0 |
T156 |
35297 |
267 |
0 |
0 |
T158 |
6162 |
7 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
4520 |
0 |
0 |
T96 |
66732 |
262 |
0 |
0 |
T99 |
17458 |
1 |
0 |
0 |
T114 |
4791 |
7 |
0 |
0 |
T115 |
10643 |
14 |
0 |
0 |
T116 |
100598 |
630 |
0 |
0 |
T120 |
73217 |
460 |
0 |
0 |
T121 |
6403 |
93 |
0 |
0 |
T122 |
7539 |
42 |
0 |
0 |
T155 |
7794 |
4 |
0 |
0 |
T158 |
6162 |
63 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
5185 |
0 |
0 |
T96 |
66732 |
665 |
0 |
0 |
T114 |
4791 |
6 |
0 |
0 |
T115 |
10643 |
77 |
0 |
0 |
T116 |
100598 |
944 |
0 |
0 |
T120 |
73217 |
427 |
0 |
0 |
T121 |
6403 |
52 |
0 |
0 |
T122 |
7539 |
78 |
0 |
0 |
T155 |
7794 |
130 |
0 |
0 |
T156 |
35297 |
289 |
0 |
0 |
T158 |
6162 |
40 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
4791 |
0 |
0 |
T96 |
66732 |
419 |
0 |
0 |
T99 |
17458 |
8 |
0 |
0 |
T114 |
4791 |
49 |
0 |
0 |
T115 |
10643 |
66 |
0 |
0 |
T116 |
100598 |
790 |
0 |
0 |
T120 |
73217 |
420 |
0 |
0 |
T121 |
6403 |
41 |
0 |
0 |
T122 |
7539 |
114 |
0 |
0 |
T155 |
7794 |
113 |
0 |
0 |
T158 |
6162 |
70 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
5008 |
0 |
0 |
T96 |
66732 |
459 |
0 |
0 |
T114 |
4791 |
54 |
0 |
0 |
T115 |
10643 |
14 |
0 |
0 |
T116 |
100598 |
806 |
0 |
0 |
T120 |
73217 |
457 |
0 |
0 |
T121 |
6403 |
66 |
0 |
0 |
T122 |
7539 |
80 |
0 |
0 |
T155 |
7794 |
58 |
0 |
0 |
T156 |
35297 |
314 |
0 |
0 |
T158 |
6162 |
9 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
4822 |
0 |
0 |
T96 |
66732 |
671 |
0 |
0 |
T114 |
4791 |
11 |
0 |
0 |
T115 |
10643 |
47 |
0 |
0 |
T116 |
100598 |
862 |
0 |
0 |
T120 |
73217 |
405 |
0 |
0 |
T121 |
6403 |
57 |
0 |
0 |
T122 |
7539 |
57 |
0 |
0 |
T155 |
7794 |
54 |
0 |
0 |
T156 |
35297 |
226 |
0 |
0 |
T158 |
6162 |
4 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
4827 |
0 |
0 |
T96 |
66732 |
572 |
0 |
0 |
T114 |
4791 |
50 |
0 |
0 |
T115 |
10643 |
56 |
0 |
0 |
T116 |
100598 |
525 |
0 |
0 |
T120 |
73217 |
510 |
0 |
0 |
T121 |
6403 |
7 |
0 |
0 |
T122 |
7539 |
46 |
0 |
0 |
T155 |
7794 |
49 |
0 |
0 |
T156 |
35297 |
340 |
0 |
0 |
T158 |
6162 |
43 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
4762 |
0 |
0 |
T96 |
66732 |
655 |
0 |
0 |
T114 |
4791 |
54 |
0 |
0 |
T115 |
10643 |
52 |
0 |
0 |
T116 |
100598 |
569 |
0 |
0 |
T120 |
73217 |
422 |
0 |
0 |
T121 |
6403 |
17 |
0 |
0 |
T122 |
7539 |
57 |
0 |
0 |
T155 |
7794 |
96 |
0 |
0 |
T156 |
35297 |
195 |
0 |
0 |
T158 |
6162 |
4 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
5269 |
0 |
0 |
T96 |
66732 |
598 |
0 |
0 |
T114 |
4791 |
4 |
0 |
0 |
T115 |
10643 |
61 |
0 |
0 |
T116 |
100598 |
761 |
0 |
0 |
T120 |
73217 |
434 |
0 |
0 |
T121 |
6403 |
6 |
0 |
0 |
T122 |
7539 |
70 |
0 |
0 |
T155 |
7794 |
115 |
0 |
0 |
T156 |
35297 |
348 |
0 |
0 |
T158 |
6162 |
44 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
4718 |
0 |
0 |
T96 |
66732 |
561 |
0 |
0 |
T99 |
17458 |
6 |
0 |
0 |
T114 |
4791 |
57 |
0 |
0 |
T115 |
10643 |
80 |
0 |
0 |
T116 |
100598 |
823 |
0 |
0 |
T120 |
73217 |
472 |
0 |
0 |
T121 |
6403 |
10 |
0 |
0 |
T122 |
7539 |
54 |
0 |
0 |
T155 |
7794 |
52 |
0 |
0 |
T158 |
6162 |
60 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
5080 |
0 |
0 |
T96 |
66732 |
602 |
0 |
0 |
T114 |
4791 |
6 |
0 |
0 |
T115 |
10643 |
17 |
0 |
0 |
T116 |
100598 |
793 |
0 |
0 |
T120 |
73217 |
459 |
0 |
0 |
T121 |
6403 |
38 |
0 |
0 |
T122 |
7539 |
47 |
0 |
0 |
T155 |
7794 |
39 |
0 |
0 |
T156 |
35297 |
296 |
0 |
0 |
T158 |
6162 |
57 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
4940 |
0 |
0 |
T96 |
66732 |
510 |
0 |
0 |
T114 |
4791 |
11 |
0 |
0 |
T115 |
10643 |
12 |
0 |
0 |
T116 |
100598 |
760 |
0 |
0 |
T120 |
73217 |
433 |
0 |
0 |
T121 |
6403 |
117 |
0 |
0 |
T122 |
7539 |
96 |
0 |
0 |
T155 |
7794 |
110 |
0 |
0 |
T156 |
35297 |
278 |
0 |
0 |
T158 |
6162 |
2 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
5071 |
0 |
0 |
T96 |
66732 |
626 |
0 |
0 |
T114 |
4791 |
33 |
0 |
0 |
T115 |
10643 |
88 |
0 |
0 |
T116 |
100598 |
913 |
0 |
0 |
T120 |
73217 |
452 |
0 |
0 |
T121 |
6403 |
69 |
0 |
0 |
T122 |
7539 |
88 |
0 |
0 |
T155 |
7794 |
4 |
0 |
0 |
T156 |
35297 |
196 |
0 |
0 |
T158 |
6162 |
35 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
4566 |
0 |
0 |
T96 |
66732 |
545 |
0 |
0 |
T114 |
4791 |
16 |
0 |
0 |
T115 |
10643 |
76 |
0 |
0 |
T116 |
100598 |
518 |
0 |
0 |
T120 |
73217 |
549 |
0 |
0 |
T121 |
6403 |
53 |
0 |
0 |
T122 |
7539 |
16 |
0 |
0 |
T155 |
7794 |
59 |
0 |
0 |
T156 |
35297 |
346 |
0 |
0 |
T158 |
6162 |
17 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
5054 |
0 |
0 |
T96 |
66732 |
826 |
0 |
0 |
T114 |
4791 |
4 |
0 |
0 |
T115 |
10643 |
97 |
0 |
0 |
T116 |
100598 |
583 |
0 |
0 |
T120 |
73217 |
502 |
0 |
0 |
T121 |
6403 |
98 |
0 |
0 |
T122 |
7539 |
63 |
0 |
0 |
T155 |
7794 |
63 |
0 |
0 |
T156 |
35297 |
188 |
0 |
0 |
T158 |
6162 |
60 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
4954 |
0 |
0 |
T96 |
66732 |
526 |
0 |
0 |
T114 |
4791 |
11 |
0 |
0 |
T115 |
10643 |
16 |
0 |
0 |
T116 |
100598 |
767 |
0 |
0 |
T120 |
73217 |
480 |
0 |
0 |
T121 |
6403 |
2 |
0 |
0 |
T122 |
7539 |
5 |
0 |
0 |
T155 |
7794 |
14 |
0 |
0 |
T156 |
35297 |
209 |
0 |
0 |
T158 |
6162 |
42 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
4868 |
0 |
0 |
T96 |
66732 |
353 |
0 |
0 |
T114 |
4791 |
12 |
0 |
0 |
T115 |
10643 |
84 |
0 |
0 |
T116 |
100598 |
1042 |
0 |
0 |
T120 |
73217 |
476 |
0 |
0 |
T121 |
6403 |
69 |
0 |
0 |
T122 |
7539 |
5 |
0 |
0 |
T155 |
7794 |
46 |
0 |
0 |
T156 |
35297 |
230 |
0 |
0 |
T158 |
6162 |
2 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
5010 |
0 |
0 |
T96 |
66732 |
728 |
0 |
0 |
T114 |
4791 |
3 |
0 |
0 |
T115 |
10643 |
56 |
0 |
0 |
T116 |
100598 |
712 |
0 |
0 |
T120 |
73217 |
488 |
0 |
0 |
T121 |
6403 |
41 |
0 |
0 |
T122 |
7539 |
75 |
0 |
0 |
T155 |
7794 |
113 |
0 |
0 |
T156 |
35297 |
211 |
0 |
0 |
T158 |
6162 |
3 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
2812 |
0 |
0 |
T96 |
66732 |
101 |
0 |
0 |
T114 |
4791 |
8 |
0 |
0 |
T115 |
10643 |
18 |
0 |
0 |
T116 |
100598 |
207 |
0 |
0 |
T120 |
73217 |
428 |
0 |
0 |
T121 |
6403 |
6 |
0 |
0 |
T122 |
7539 |
6 |
0 |
0 |
T155 |
7794 |
19 |
0 |
0 |
T156 |
35297 |
62 |
0 |
0 |
T158 |
6162 |
7 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
2767 |
0 |
0 |
T96 |
66732 |
124 |
0 |
0 |
T103 |
16222 |
8 |
0 |
0 |
T114 |
4791 |
11 |
0 |
0 |
T115 |
10643 |
30 |
0 |
0 |
T116 |
100598 |
107 |
0 |
0 |
T120 |
73217 |
443 |
0 |
0 |
T121 |
6403 |
20 |
0 |
0 |
T122 |
7539 |
17 |
0 |
0 |
T155 |
7794 |
6 |
0 |
0 |
T158 |
6162 |
13 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
2551 |
0 |
0 |
T96 |
66732 |
90 |
0 |
0 |
T114 |
4791 |
19 |
0 |
0 |
T115 |
10643 |
33 |
0 |
0 |
T116 |
100598 |
141 |
0 |
0 |
T120 |
73217 |
436 |
0 |
0 |
T121 |
6403 |
9 |
0 |
0 |
T122 |
7539 |
11 |
0 |
0 |
T155 |
7794 |
11 |
0 |
0 |
T156 |
35297 |
44 |
0 |
0 |
T158 |
6162 |
12 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
2733 |
0 |
0 |
T96 |
66732 |
106 |
0 |
0 |
T114 |
4791 |
4 |
0 |
0 |
T115 |
10643 |
16 |
0 |
0 |
T116 |
100598 |
146 |
0 |
0 |
T120 |
73217 |
487 |
0 |
0 |
T121 |
6403 |
15 |
0 |
0 |
T122 |
7539 |
13 |
0 |
0 |
T155 |
7794 |
9 |
0 |
0 |
T156 |
35297 |
67 |
0 |
0 |
T158 |
6162 |
17 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
3174 |
0 |
0 |
T96 |
66732 |
256 |
0 |
0 |
T99 |
17458 |
6 |
0 |
0 |
T114 |
4791 |
7 |
0 |
0 |
T115 |
10643 |
12 |
0 |
0 |
T116 |
100598 |
286 |
0 |
0 |
T120 |
73217 |
439 |
0 |
0 |
T121 |
6403 |
4 |
0 |
0 |
T122 |
7539 |
21 |
0 |
0 |
T155 |
7794 |
51 |
0 |
0 |
T158 |
6162 |
9 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
4608 |
0 |
0 |
T19 |
668222 |
11 |
0 |
0 |
T20 |
0 |
53 |
0 |
0 |
T90 |
853953 |
0 |
0 |
0 |
T130 |
1631 |
0 |
0 |
0 |
T131 |
329355 |
0 |
0 |
0 |
T132 |
1731 |
0 |
0 |
0 |
T133 |
633475 |
0 |
0 |
0 |
T134 |
208440 |
0 |
0 |
0 |
T135 |
313689 |
0 |
0 |
0 |
T136 |
659544 |
0 |
0 |
0 |
T137 |
2865 |
0 |
0 |
0 |
T159 |
0 |
5 |
0 |
0 |
T160 |
0 |
61 |
0 |
0 |
T161 |
0 |
29 |
0 |
0 |
T162 |
0 |
77 |
0 |
0 |
T163 |
0 |
69 |
0 |
0 |
T164 |
0 |
14 |
0 |
0 |
T165 |
0 |
11 |
0 |
0 |
T166 |
0 |
11 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
2773 |
0 |
0 |
T96 |
66732 |
142 |
0 |
0 |
T114 |
4791 |
14 |
0 |
0 |
T115 |
10643 |
22 |
0 |
0 |
T116 |
100598 |
217 |
0 |
0 |
T120 |
73217 |
506 |
0 |
0 |
T121 |
6403 |
9 |
0 |
0 |
T122 |
7539 |
9 |
0 |
0 |
T155 |
7794 |
6 |
0 |
0 |
T156 |
35297 |
54 |
0 |
0 |
T158 |
6162 |
13 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
2787 |
0 |
0 |
T96 |
66732 |
133 |
0 |
0 |
T114 |
4791 |
20 |
0 |
0 |
T115 |
10643 |
22 |
0 |
0 |
T116 |
100598 |
153 |
0 |
0 |
T120 |
73217 |
475 |
0 |
0 |
T121 |
6403 |
5 |
0 |
0 |
T122 |
7539 |
11 |
0 |
0 |
T155 |
7794 |
15 |
0 |
0 |
T156 |
35297 |
60 |
0 |
0 |
T158 |
6162 |
8 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
2444 |
0 |
0 |
T96 |
66732 |
85 |
0 |
0 |
T99 |
17458 |
4 |
0 |
0 |
T114 |
4791 |
4 |
0 |
0 |
T115 |
10643 |
10 |
0 |
0 |
T116 |
100598 |
100 |
0 |
0 |
T120 |
73217 |
432 |
0 |
0 |
T121 |
6403 |
4 |
0 |
0 |
T122 |
7539 |
13 |
0 |
0 |
T155 |
7794 |
11 |
0 |
0 |
T158 |
6162 |
8 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
2451 |
0 |
0 |
T96 |
66732 |
90 |
0 |
0 |
T114 |
4791 |
1 |
0 |
0 |
T115 |
10643 |
13 |
0 |
0 |
T116 |
100598 |
100 |
0 |
0 |
T120 |
73217 |
445 |
0 |
0 |
T121 |
6403 |
15 |
0 |
0 |
T122 |
7539 |
13 |
0 |
0 |
T155 |
7794 |
6 |
0 |
0 |
T156 |
35297 |
29 |
0 |
0 |
T158 |
6162 |
1 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
2450 |
0 |
0 |
T96 |
66732 |
75 |
0 |
0 |
T115 |
10643 |
19 |
0 |
0 |
T116 |
100598 |
110 |
0 |
0 |
T120 |
73217 |
441 |
0 |
0 |
T121 |
6403 |
5 |
0 |
0 |
T122 |
7539 |
14 |
0 |
0 |
T155 |
7794 |
12 |
0 |
0 |
T156 |
35297 |
51 |
0 |
0 |
T157 |
6960 |
6 |
0 |
0 |
T158 |
6162 |
6 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
2431 |
0 |
0 |
T96 |
66732 |
48 |
0 |
0 |
T114 |
4791 |
5 |
0 |
0 |
T115 |
10643 |
7 |
0 |
0 |
T116 |
100598 |
97 |
0 |
0 |
T120 |
73217 |
468 |
0 |
0 |
T121 |
6403 |
12 |
0 |
0 |
T122 |
7539 |
4 |
0 |
0 |
T155 |
7794 |
5 |
0 |
0 |
T156 |
35297 |
44 |
0 |
0 |
T158 |
6162 |
11 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
3283 |
0 |
0 |
T96 |
66732 |
239 |
0 |
0 |
T114 |
4791 |
19 |
0 |
0 |
T115 |
10643 |
40 |
0 |
0 |
T116 |
100598 |
282 |
0 |
0 |
T120 |
73217 |
454 |
0 |
0 |
T121 |
6403 |
8 |
0 |
0 |
T122 |
7539 |
11 |
0 |
0 |
T155 |
7794 |
23 |
0 |
0 |
T156 |
35297 |
63 |
0 |
0 |
T158 |
6162 |
7 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
2390 |
0 |
0 |
T96 |
66732 |
70 |
0 |
0 |
T114 |
4791 |
7 |
0 |
0 |
T115 |
10643 |
17 |
0 |
0 |
T116 |
100598 |
107 |
0 |
0 |
T120 |
73217 |
490 |
0 |
0 |
T121 |
6403 |
4 |
0 |
0 |
T122 |
7539 |
4 |
0 |
0 |
T155 |
7794 |
3 |
0 |
0 |
T156 |
35297 |
40 |
0 |
0 |
T158 |
6162 |
13 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
3179 |
0 |
0 |
T96 |
66732 |
193 |
0 |
0 |
T114 |
4791 |
7 |
0 |
0 |
T115 |
10643 |
37 |
0 |
0 |
T116 |
100598 |
282 |
0 |
0 |
T120 |
73217 |
410 |
0 |
0 |
T121 |
6403 |
20 |
0 |
0 |
T122 |
7539 |
32 |
0 |
0 |
T155 |
7794 |
7 |
0 |
0 |
T156 |
35297 |
85 |
0 |
0 |
T158 |
6162 |
8 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
2777 |
0 |
0 |
T96 |
66732 |
152 |
0 |
0 |
T114 |
4791 |
14 |
0 |
0 |
T115 |
10643 |
19 |
0 |
0 |
T116 |
100598 |
169 |
0 |
0 |
T120 |
73217 |
476 |
0 |
0 |
T121 |
6403 |
6 |
0 |
0 |
T122 |
7539 |
11 |
0 |
0 |
T155 |
7794 |
14 |
0 |
0 |
T156 |
35297 |
55 |
0 |
0 |
T158 |
6162 |
10 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
2382 |
0 |
0 |
T96 |
66732 |
63 |
0 |
0 |
T114 |
4791 |
7 |
0 |
0 |
T115 |
10643 |
19 |
0 |
0 |
T116 |
100598 |
110 |
0 |
0 |
T120 |
73217 |
402 |
0 |
0 |
T121 |
6403 |
7 |
0 |
0 |
T122 |
7539 |
3 |
0 |
0 |
T155 |
7794 |
7 |
0 |
0 |
T156 |
35297 |
38 |
0 |
0 |
T158 |
6162 |
6 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
2665 |
0 |
0 |
T96 |
66732 |
87 |
0 |
0 |
T114 |
4791 |
17 |
0 |
0 |
T115 |
10643 |
11 |
0 |
0 |
T116 |
100598 |
106 |
0 |
0 |
T120 |
73217 |
453 |
0 |
0 |
T121 |
6403 |
11 |
0 |
0 |
T122 |
7539 |
8 |
0 |
0 |
T155 |
7794 |
11 |
0 |
0 |
T156 |
35297 |
37 |
0 |
0 |
T158 |
6162 |
6 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
2570 |
0 |
0 |
T96 |
66732 |
61 |
0 |
0 |
T114 |
4791 |
4 |
0 |
0 |
T115 |
10643 |
14 |
0 |
0 |
T116 |
100598 |
112 |
0 |
0 |
T120 |
73217 |
536 |
0 |
0 |
T121 |
6403 |
3 |
0 |
0 |
T122 |
7539 |
8 |
0 |
0 |
T155 |
7794 |
3 |
0 |
0 |
T156 |
35297 |
39 |
0 |
0 |
T158 |
6162 |
4 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
2461 |
0 |
0 |
T96 |
66732 |
75 |
0 |
0 |
T114 |
4791 |
8 |
0 |
0 |
T115 |
10643 |
18 |
0 |
0 |
T116 |
100598 |
137 |
0 |
0 |
T120 |
73217 |
403 |
0 |
0 |
T121 |
6403 |
5 |
0 |
0 |
T122 |
7539 |
5 |
0 |
0 |
T155 |
7794 |
9 |
0 |
0 |
T156 |
35297 |
37 |
0 |
0 |
T158 |
6162 |
8 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
2516 |
0 |
0 |
T96 |
66732 |
66 |
0 |
0 |
T114 |
4791 |
7 |
0 |
0 |
T115 |
10643 |
4 |
0 |
0 |
T116 |
100598 |
122 |
0 |
0 |
T120 |
73217 |
479 |
0 |
0 |
T121 |
6403 |
1 |
0 |
0 |
T122 |
7539 |
11 |
0 |
0 |
T155 |
7794 |
5 |
0 |
0 |
T156 |
35297 |
36 |
0 |
0 |
T158 |
6162 |
11 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471903602 |
2605 |
0 |
0 |
T96 |
66732 |
82 |
0 |
0 |
T114 |
4791 |
12 |
0 |
0 |
T115 |
10643 |
13 |
0 |
0 |
T116 |
100598 |
114 |
0 |
0 |
T120 |
73217 |
518 |
0 |
0 |
T121 |
6403 |
9 |
0 |
0 |
T122 |
7539 |
6 |
0 |
0 |
T155 |
7794 |
3 |
0 |
0 |
T156 |
35297 |
47 |
0 |
0 |
T158 |
6162 |
14 |
0 |
0 |