Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3609265	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4221656

1

T1

4730

T3

12518

T4

142

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4285650	1			T1	611		T2	79		T3	3756
values[0x0]	1770109	1			T1	2226		T3	5314		T4	65
values[0x1]	1775162	1			T1	2173		T3	5255		T4	59

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2557128	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5273793

1

T1

4797

T2

18

T3

12920

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28140	1			T1	14		T3	45		T7	33
valid_sources[0x01]	27232	1			T1	15		T2	6		T3	64
valid_sources[0x02]	29016	1			T1	14		T3	50		T7	34
valid_sources[0x03]	29475	1			T1	37		T3	66		T6	1
valid_sources[0x04]	29112	1			T1	32		T3	62		T6	1
valid_sources[0x05]	27329	1			T1	14		T3	78		T7	53
valid_sources[0x06]	26175	1			T1	18		T3	48		T6	1
valid_sources[0x07]	26886	1			T1	11		T3	48		T6	16
valid_sources[0x08]	30678	1			T1	17		T3	49		T7	42
valid_sources[0x09]	31641	1			T1	18		T2	9		T3	44
valid_sources[0x0a]	31512	1			T1	20		T3	60		T7	11
valid_sources[0x0b]	29515	1			T1	14		T3	67		T7	34
valid_sources[0x0c]	29653	1			T1	9		T3	62		T7	25
valid_sources[0x0d]	33165	1			T1	17		T3	52		T6	2
valid_sources[0x0e]	30577	1			T1	24		T3	67		T7	35
valid_sources[0x0f]	30111	1			T1	21		T3	43		T7	39
valid_sources[0x10]	30635	1			T1	20		T3	44		T7	47
valid_sources[0x11]	29482	1			T1	11		T3	39		T7	33
valid_sources[0x12]	28665	1			T1	22		T3	81		T7	47
valid_sources[0x13]	27806	1			T1	15		T3	47		T6	416
valid_sources[0x14]	28054	1			T1	18		T3	49		T7	29
valid_sources[0x15]	28506	1			T1	12		T3	52		T7	27
valid_sources[0x16]	26291	1			T1	23		T2	1		T3	39
valid_sources[0x17]	26944	1			T1	21		T3	72		T7	15
valid_sources[0x18]	28847	1			T1	23		T3	57		T7	29
valid_sources[0x19]	29342	1			T1	8		T3	40		T7	11
valid_sources[0x1a]	29688	1			T1	18		T2	2		T3	57
valid_sources[0x1b]	29345	1			T1	30		T3	71		T7	25
valid_sources[0x1c]	31094	1			T1	23		T3	48		T7	44
valid_sources[0x1d]	26076	1			T1	24		T3	60		T7	48
valid_sources[0x1e]	29346	1			T1	33		T3	67		T7	35
valid_sources[0x1f]	28666	1			T1	27		T3	56		T7	38
valid_sources[0x20]	27643	1			T1	21		T3	56		T7	57
valid_sources[0x21]	29715	1			T1	10		T2	8		T3	61
valid_sources[0x22]	28157	1			T1	12		T3	48		T7	28
valid_sources[0x23]	31348	1			T1	20		T3	60		T7	37
valid_sources[0x24]	31498	1			T1	5		T3	61		T7	22
valid_sources[0x25]	28524	1			T1	16		T3	42		T7	22
valid_sources[0x26]	30227	1			T1	23		T3	63		T7	42
valid_sources[0x27]	32139	1			T1	11		T3	59		T7	70
valid_sources[0x28]	29418	1			T1	10		T2	1		T3	56
valid_sources[0x29]	27842	1			T1	23		T3	52		T6	416
valid_sources[0x2a]	28192	1			T1	23		T3	46		T7	34
valid_sources[0x2b]	27901	1			T1	8		T3	66		T7	21
valid_sources[0x2c]	28239	1			T1	12		T3	57		T7	32
valid_sources[0x2d]	39146	1			T1	9		T2	1		T3	57
valid_sources[0x2e]	28814	1			T1	17		T3	83		T7	27
valid_sources[0x2f]	30544	1			T1	18		T3	37		T6	961
valid_sources[0x30]	29358	1			T1	31		T2	2		T3	50
valid_sources[0x31]	29303	1			T1	15		T3	65		T7	23
valid_sources[0x32]	28477	1			T1	15		T3	65		T7	52
valid_sources[0x33]	27141	1			T1	26		T3	73		T7	28
valid_sources[0x34]	27719	1			T1	21		T3	44		T7	59
valid_sources[0x35]	31123	1			T1	12		T3	52		T7	27
valid_sources[0x36]	26199	1			T1	31		T3	44		T7	31
valid_sources[0x37]	30613	1			T1	18		T3	58		T7	50
valid_sources[0x38]	29971	1			T1	59		T3	51		T7	32
valid_sources[0x39]	28645	1			T1	23		T3	48		T7	16
valid_sources[0x3a]	30980	1			T1	15		T2	1		T3	69
valid_sources[0x3b]	27434	1			T1	9		T3	54		T6	389
valid_sources[0x3c]	32571	1			T1	35		T3	70		T7	35
valid_sources[0x3d]	32013	1			T1	27		T3	77		T7	22
valid_sources[0x3e]	29392	1			T1	8		T3	37		T7	21
valid_sources[0x3f]	29180	1			T1	30		T3	53		T7	14
valid_sources[0x40]	32816	1			T1	22		T2	3		T3	68
valid_sources[0x41]	29421	1			T1	7		T3	43		T6	24
valid_sources[0x42]	29662	1			T1	21		T3	82		T7	27
valid_sources[0x43]	30237	1			T1	25		T3	63		T7	21
valid_sources[0x44]	27679	1			T1	41		T2	2		T3	61
valid_sources[0x45]	31521	1			T1	16		T3	94		T7	37
valid_sources[0x46]	27671	1			T1	18		T3	44		T7	27
valid_sources[0x47]	29589	1			T1	15		T3	61		T7	52
valid_sources[0x48]	31455	1			T1	14		T3	74		T7	34
valid_sources[0x49]	51995	1			T1	30		T3	56		T7	31
valid_sources[0x4a]	28683	1			T1	34		T3	48		T7	30
valid_sources[0x4b]	26654	1			T1	10		T3	59		T7	43
valid_sources[0x4c]	30750	1			T1	18		T3	53		T7	43
valid_sources[0x4d]	32849	1			T1	24		T3	72		T7	48
valid_sources[0x4e]	30120	1			T1	17		T2	1		T3	55
valid_sources[0x4f]	28864	1			T1	19		T3	44		T7	58
valid_sources[0x50]	28275	1			T1	50		T3	63		T7	42
valid_sources[0x51]	34590	1			T1	23		T3	56		T6	1
valid_sources[0x52]	28824	1			T1	16		T3	32		T7	32
valid_sources[0x53]	33273	1			T1	25		T3	67		T7	45
valid_sources[0x54]	35789	1			T1	24		T3	72		T6	1
valid_sources[0x55]	26925	1			T1	25		T3	70		T6	48
valid_sources[0x56]	29033	1			T1	16		T3	72		T7	47
valid_sources[0x57]	28339	1			T1	13		T3	53		T7	30
valid_sources[0x58]	30635	1			T1	13		T3	74		T7	18
valid_sources[0x59]	31399	1			T1	12		T3	65		T7	66
valid_sources[0x5a]	30745	1			T1	25		T3	72		T6	2
valid_sources[0x5b]	28013	1			T1	17		T3	46		T7	40
valid_sources[0x5c]	35358	1			T1	23		T3	59		T7	22
valid_sources[0x5d]	32950	1			T1	14		T3	43		T6	72
valid_sources[0x5e]	29700	1			T1	27		T3	42		T7	24
valid_sources[0x5f]	27349	1			T1	16		T3	59		T7	12
valid_sources[0x60]	28376	1			T1	24		T3	51		T7	43
valid_sources[0x61]	31332	1			T1	12		T3	62		T7	32
valid_sources[0x62]	27939	1			T1	16		T3	87		T7	49
valid_sources[0x63]	29426	1			T1	22		T3	55		T7	25
valid_sources[0x64]	28602	1			T1	27		T3	74		T7	47
valid_sources[0x65]	27507	1			T1	24		T3	58		T7	50
valid_sources[0x66]	28243	1			T1	22		T3	59		T7	39
valid_sources[0x67]	29228	1			T1	15		T3	76		T6	1
valid_sources[0x68]	30813	1			T1	16		T3	52		T7	29
valid_sources[0x69]	31395	1			T1	15		T3	79		T7	34
valid_sources[0x6a]	27237	1			T1	44		T3	37		T7	29
valid_sources[0x6b]	31557	1			T1	23		T3	33		T7	24
valid_sources[0x6c]	29548	1			T1	11		T3	62		T7	22
valid_sources[0x6d]	27817	1			T1	31		T3	47		T7	63
valid_sources[0x6e]	27546	1			T1	8		T3	38		T7	22
valid_sources[0x6f]	39779	1			T1	18		T3	70		T6	2
valid_sources[0x70]	28424	1			T1	17		T2	2		T3	62
valid_sources[0x71]	64475	1			T1	13		T3	64		T7	21
valid_sources[0x72]	31930	1			T1	24		T3	42		T7	54
valid_sources[0x73]	27843	1			T1	33		T3	58		T6	1
valid_sources[0x74]	34111	1			T1	33		T3	57		T7	20
valid_sources[0x75]	30559	1			T1	21		T2	5		T3	62
valid_sources[0x76]	35306	1			T1	21		T2	2		T3	42
valid_sources[0x77]	33537	1			T1	13		T3	37		T6	1
valid_sources[0x78]	31449	1			T1	9		T2	3		T3	70
valid_sources[0x79]	36796	1			T1	20		T3	59		T7	49
valid_sources[0x7a]	28170	1			T1	22		T3	50		T7	33
valid_sources[0x7b]	32200	1			T1	33		T3	60		T7	33
valid_sources[0x7c]	26665	1			T1	26		T3	40		T7	28
valid_sources[0x7d]	31586	1			T1	16		T3	69		T7	23
valid_sources[0x7e]	32774	1			T1	15		T3	31		T6	1534
valid_sources[0x7f]	53030	1			T1	14		T2	4		T3	67
valid_sources[0x80]	28055	1			T1	18		T3	51		T7	33

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1015507

1

T1

355

T3

1994

T4

58

values[0x0]

all_enables

biggest_size

1613228

1

T1

2221

T3

5297

T4

45

values[0x1]

all_enables

biggest_size

1592921

1

T1

2154

T3

5227

T4

39