Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
3626205 |
1 |
|
|
T1 |
280 |
|
T2 |
79 |
|
T3 |
1807 |
full_word |
4222646 |
1 |
|
|
T1 |
4730 |
|
T3 |
12518 |
|
T4 |
142 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
7848491 |
1 |
|
|
T1 |
5010 |
|
T2 |
79 |
|
T3 |
14325 |
auto[TlIntgErrCmd] |
107 |
1 |
|
|
T69 |
10 |
|
T71 |
2 |
|
T94 |
6 |
auto[TlIntgErrData] |
126 |
1 |
|
|
T69 |
5 |
|
T71 |
2 |
|
T94 |
7 |
auto[TlIntgErrBoth] |
127 |
1 |
|
|
T69 |
5 |
|
T71 |
6 |
|
T94 |
7 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4288446 |
1 |
|
|
T1 |
611 |
|
T2 |
79 |
|
T3 |
3756 |
auto[1] |
3560405 |
1 |
|
|
T1 |
4399 |
|
T3 |
10569 |
|
T4 |
124 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
3272533 |
1 |
|
|
T1 |
256 |
|
T2 |
79 |
|
T3 |
1762 |
auto[TlIntgErrNone] |
partial |
auto[1] |
353337 |
1 |
|
|
T1 |
24 |
|
T3 |
45 |
|
T4 |
40 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
1015749 |
1 |
|
|
T1 |
355 |
|
T3 |
1994 |
|
T4 |
58 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
3206872 |
1 |
|
|
T1 |
4375 |
|
T3 |
10524 |
|
T4 |
84 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
49 |
1 |
|
|
T69 |
4 |
|
T71 |
1 |
|
T94 |
3 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
51 |
1 |
|
|
T69 |
6 |
|
T94 |
3 |
|
T182 |
2 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
3 |
1 |
|
|
T186 |
1 |
|
T187 |
2 |
|
- |
- |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
4 |
1 |
|
|
T71 |
1 |
|
T188 |
1 |
|
T189 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
60 |
1 |
|
|
T69 |
1 |
|
T71 |
2 |
|
T94 |
4 |
auto[TlIntgErrData] |
partial |
auto[1] |
54 |
1 |
|
|
T69 |
4 |
|
T94 |
2 |
|
T186 |
2 |
auto[TlIntgErrData] |
full_word |
auto[0] |
5 |
1 |
|
|
T190 |
1 |
|
T191 |
2 |
|
T192 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
7 |
1 |
|
|
T94 |
1 |
|
T190 |
1 |
|
T183 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
46 |
1 |
|
|
T71 |
2 |
|
T94 |
2 |
|
T182 |
2 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
75 |
1 |
|
|
T69 |
5 |
|
T71 |
4 |
|
T94 |
5 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
1 |
1 |
|
|
T183 |
1 |
|
- |
- |
|
- |
- |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
5 |
1 |
|
|
T193 |
1 |
|
T194 |
2 |
|
T192 |
1 |