Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
partial 3626205 1 T1 280 T2 79 T3 1807
full_word 4222646 1 T1 4730 T3 12518 T4 142



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 7848491 1 T1 5010 T2 79 T3 14325
auto[TlIntgErrCmd] 107 1 T69 10 T71 2 T94 6
auto[TlIntgErrData] 126 1 T69 5 T71 2 T94 7
auto[TlIntgErrBoth] 127 1 T69 5 T71 6 T94 7



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4288446 1 T1 611 T2 79 T3 3756
auto[1] 3560405 1 T1 4399 T3 10569 T4 124



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 3272533 1 T1 256 T2 79 T3 1762
auto[TlIntgErrNone] partial auto[1] 353337 1 T1 24 T3 45 T4 40
auto[TlIntgErrNone] full_word auto[0] 1015749 1 T1 355 T3 1994 T4 58
auto[TlIntgErrNone] full_word auto[1] 3206872 1 T1 4375 T3 10524 T4 84
auto[TlIntgErrCmd] partial auto[0] 49 1 T69 4 T71 1 T94 3
auto[TlIntgErrCmd] partial auto[1] 51 1 T69 6 T94 3 T182 2
auto[TlIntgErrCmd] full_word auto[0] 3 1 T186 1 T187 2 - -
auto[TlIntgErrCmd] full_word auto[1] 4 1 T71 1 T188 1 T189 1
auto[TlIntgErrData] partial auto[0] 60 1 T69 1 T71 2 T94 4
auto[TlIntgErrData] partial auto[1] 54 1 T69 4 T94 2 T186 2
auto[TlIntgErrData] full_word auto[0] 5 1 T190 1 T191 2 T192 1
auto[TlIntgErrData] full_word auto[1] 7 1 T94 1 T190 1 T183 1
auto[TlIntgErrBoth] partial auto[0] 46 1 T71 2 T94 2 T182 2
auto[TlIntgErrBoth] partial auto[1] 75 1 T69 5 T71 4 T94 5
auto[TlIntgErrBoth] full_word auto[0] 1 1 T183 1 - - - -
auto[TlIntgErrBoth] full_word auto[1] 5 1 T193 1 T194 2 T192 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%