Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	603140883	3308101	0	0
gen_wmask[1].MaskCheckPortA_A	603140883	3308101	0	0
gen_wmask[2].MaskCheckPortA_A	603140883	3308101	0	0
gen_wmask[3].MaskCheckPortA_A	603140883	3308101	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603140883	3308101	0	0
T1	356010	4422	0	0
T2	1921	0	0	0
T3	650442	17320	0	0
T4	11759	243	0	0
T5	1118	0	0	0
T6	732764	16289	0	0
T7	507279	9776	0	0
T8	508890	832	0	0
T9	73389	832	0	0
T10	85345	832	0	0
T11	199375	2759	0	0
T12	16536	832	0	0
T28	0	9346	0	0
T30	0	16854	0	0
T31	0	3126	0	0
T40	0	1534	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603140883	3308101	0	0
T1	356010	4422	0	0
T2	1921	0	0	0
T3	650442	17320	0	0
T4	11759	243	0	0
T5	1118	0	0	0
T6	732764	16289	0	0
T7	507279	9776	0	0
T8	508890	832	0	0
T9	73389	832	0	0
T10	85345	832	0	0
T11	199375	2759	0	0
T12	16536	832	0	0
T28	0	9346	0	0
T30	0	16854	0	0
T31	0	3126	0	0
T40	0	1534	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603140883	3308101	0	0
T1	356010	4422	0	0
T2	1921	0	0	0
T3	650442	17320	0	0
T4	11759	243	0	0
T5	1118	0	0	0
T6	732764	16289	0	0
T7	507279	9776	0	0
T8	508890	832	0	0
T9	73389	832	0	0
T10	85345	832	0	0
T11	199375	2759	0	0
T12	16536	832	0	0
T28	0	9346	0	0
T30	0	16854	0	0
T31	0	3126	0	0
T40	0	1534	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	603140883	3308101	0	0
T1	356010	4422	0	0
T2	1921	0	0	0
T3	650442	17320	0	0
T4	11759	243	0	0
T5	1118	0	0	0
T6	732764	16289	0	0
T7	507279	9776	0	0
T8	508890	832	0	0
T9	73389	832	0	0
T10	85345	832	0	0
T11	199375	2759	0	0
T12	16536	832	0	0
T28	0	9346	0	0
T30	0	16854	0	0
T31	0	3126	0	0
T40	0	1534	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	455939979	2066565	0	0
gen_wmask[1].MaskCheckPortA_A	455939979	2066565	0	0
gen_wmask[2].MaskCheckPortA_A	455939979	2066565	0	0
gen_wmask[3].MaskCheckPortA_A	455939979	2066565	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455939979	2066565	0	0
T1	193573	4160	0	0
T2	1921	0	0	0
T3	223188	9984	0	0
T4	5152	59	0	0
T5	1118	0	0	0
T6	258835	11648	0	0
T7	172521	7488	0	0
T8	453209	832	0	0
T9	60845	832	0	0
T10	68913	832	0	0
T11	0	2496	0	0
T12	0	832	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455939979	2066565	0	0
T1	193573	4160	0	0
T2	1921	0	0	0
T3	223188	9984	0	0
T4	5152	59	0	0
T5	1118	0	0	0
T6	258835	11648	0	0
T7	172521	7488	0	0
T8	453209	832	0	0
T9	60845	832	0	0
T10	68913	832	0	0
T11	0	2496	0	0
T12	0	832	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455939979	2066565	0	0
T1	193573	4160	0	0
T2	1921	0	0	0
T3	223188	9984	0	0
T4	5152	59	0	0
T5	1118	0	0	0
T6	258835	11648	0	0
T7	172521	7488	0	0
T8	453209	832	0	0
T9	60845	832	0	0
T10	68913	832	0	0
T11	0	2496	0	0
T12	0	832	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455939979	2066565	0	0
T1	193573	4160	0	0
T2	1921	0	0	0
T3	223188	9984	0	0
T4	5152	59	0	0
T5	1118	0	0	0
T6	258835	11648	0	0
T7	172521	7488	0	0
T8	453209	832	0	0
T9	60845	832	0	0
T10	68913	832	0	0
T11	0	2496	0	0
T12	0	832	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	147200904	1241536	0	0
gen_wmask[1].MaskCheckPortA_A	147200904	1241536	0	0
gen_wmask[2].MaskCheckPortA_A	147200904	1241536	0	0
gen_wmask[3].MaskCheckPortA_A	147200904	1241536	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	1241536	0	0
T1	162437	262	0	0
T3	427254	7336	0	0
T4	6607	184	0	0
T6	473929	4641	0	0
T7	334758	2288	0	0
T8	55681	0	0	0
T9	12544	0	0	0
T10	16432	0	0	0
T11	199375	263	0	0
T12	16536	0	0	0
T28	0	9346	0	0
T30	0	16854	0	0
T31	0	3126	0	0
T40	0	1534	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	1241536	0	0
T1	162437	262	0	0
T3	427254	7336	0	0
T4	6607	184	0	0
T6	473929	4641	0	0
T7	334758	2288	0	0
T8	55681	0	0	0
T9	12544	0	0	0
T10	16432	0	0	0
T11	199375	263	0	0
T12	16536	0	0	0
T28	0	9346	0	0
T30	0	16854	0	0
T31	0	3126	0	0
T40	0	1534	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	1241536	0	0
T1	162437	262	0	0
T3	427254	7336	0	0
T4	6607	184	0	0
T6	473929	4641	0	0
T7	334758	2288	0	0
T8	55681	0	0	0
T9	12544	0	0	0
T10	16432	0	0	0
T11	199375	263	0	0
T12	16536	0	0	0
T28	0	9346	0	0
T30	0	16854	0	0
T31	0	3126	0	0
T40	0	1534	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	1241536	0	0
T1	162437	262	0	0
T3	427254	7336	0	0
T4	6607	184	0	0
T6	473929	4641	0	0
T7	334758	2288	0	0
T8	55681	0	0	0
T9	12544	0	0	0
T10	16432	0	0	0
T11	199375	263	0	0
T12	16536	0	0	0
T28	0	9346	0	0
T30	0	16854	0	0
T31	0	3126	0	0
T40	0	1534	0	0