Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	458380983	2848067	0	0
DepthKnown_A	458380983	458253414	0	0
RvalidKnown_A	458380983	458253414	0	0
WreadyKnown_A	458380983	458253414	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2848067	0	0
T1	193573	6653	0	0
T2	1921	0	0	0
T3	223188	13321	0	0
T4	5152	0	0	0
T5	1118	0	0	0
T6	258835	17465	0	0
T7	172521	11648	0	0
T8	453209	832	0	0
T9	60845	832	0	0
T10	68913	832	0	0
T11	0	4165	0	0
T12	0	832	0	0
T13	0	4729	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	458253414	0	0
T1	193573	193504	0	0
T2	1921	1828	0	0
T3	223188	223182	0	0
T4	5152	5100	0	0
T5	1118	1036	0	0
T6	258835	258746	0	0
T7	172521	172460	0	0
T8	453209	453155	0	0
T9	60845	60774	0	0
T10	68913	68813	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	458253414	0	0
T1	193573	193504	0	0
T2	1921	1828	0	0
T3	223188	223182	0	0
T4	5152	5100	0	0
T5	1118	1036	0	0
T6	258835	258746	0	0
T7	172521	172460	0	0
T8	453209	453155	0	0
T9	60845	60774	0	0
T10	68913	68813	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	458253414	0	0
T1	193573	193504	0	0
T2	1921	1828	0	0
T3	223188	223182	0	0
T4	5152	5100	0	0
T5	1118	1036	0	0
T6	258835	258746	0	0
T7	172521	172460	0	0
T8	453209	453155	0	0
T9	60845	60774	0	0
T10	68913	68813	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	458380983	3151083	0	0
DepthKnown_A	458380983	458253414	0	0
RvalidKnown_A	458380983	458253414	0	0
WreadyKnown_A	458380983	458253414	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	3151083	0	0
T1	193573	4160	0	0
T2	1921	0	0	0
T3	223188	33460	0	0
T4	5152	0	0	0
T5	1118	0	0	0
T6	258835	11648	0	0
T7	172521	14796	0	0
T8	453209	2607	0	0
T9	60845	3774	0	0
T10	68913	832	0	0
T11	0	5390	0	0
T12	0	832	0	0
T13	0	2368	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	458253414	0	0
T1	193573	193504	0	0
T2	1921	1828	0	0
T3	223188	223182	0	0
T4	5152	5100	0	0
T5	1118	1036	0	0
T6	258835	258746	0	0
T7	172521	172460	0	0
T8	453209	453155	0	0
T9	60845	60774	0	0
T10	68913	68813	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	458253414	0	0
T1	193573	193504	0	0
T2	1921	1828	0	0
T3	223188	223182	0	0
T4	5152	5100	0	0
T5	1118	1036	0	0
T6	258835	258746	0	0
T7	172521	172460	0	0
T8	453209	453155	0	0
T9	60845	60774	0	0
T10	68913	68813	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	458253414	0	0
T1	193573	193504	0	0
T2	1921	1828	0	0
T3	223188	223182	0	0
T4	5152	5100	0	0
T5	1118	1036	0	0
T6	258835	258746	0	0
T7	172521	172460	0	0
T8	453209	453155	0	0
T9	60845	60774	0	0
T10	68913	68813	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	458380983	189573	0	0
DepthKnown_A	458380983	458253414	0	0
RvalidKnown_A	458380983	458253414	0	0
WreadyKnown_A	458380983	458253414	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	189573	0	0
T1	193573	64	0	0
T2	1921	0	0	0
T3	223188	289	0	0
T4	5152	49	0	0
T5	1118	0	0	0
T6	258835	483	0	0
T7	172521	488	0	0
T8	453209	0	0	0
T9	60845	0	0	0
T10	68913	0	0	0
T11	0	64	0	0
T28	0	480	0	0
T30	0	1032	0	0
T31	0	817	0	0
T40	0	307	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	458253414	0	0
T1	193573	193504	0	0
T2	1921	1828	0	0
T3	223188	223182	0	0
T4	5152	5100	0	0
T5	1118	1036	0	0
T6	258835	258746	0	0
T7	172521	172460	0	0
T8	453209	453155	0	0
T9	60845	60774	0	0
T10	68913	68813	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	458253414	0	0
T1	193573	193504	0	0
T2	1921	1828	0	0
T3	223188	223182	0	0
T4	5152	5100	0	0
T5	1118	1036	0	0
T6	258835	258746	0	0
T7	172521	172460	0	0
T8	453209	453155	0	0
T9	60845	60774	0	0
T10	68913	68813	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	458253414	0	0
T1	193573	193504	0	0
T2	1921	1828	0	0
T3	223188	223182	0	0
T4	5152	5100	0	0
T5	1118	1036	0	0
T6	258835	258746	0	0
T7	172521	172460	0	0
T8	453209	453155	0	0
T9	60845	60774	0	0
T10	68913	68813	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	458380983	432810	0	0
DepthKnown_A	458380983	458253414	0	0
RvalidKnown_A	458380983	458253414	0	0
WreadyKnown_A	458380983	458253414	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	432810	0	0
T1	193573	64	0	0
T2	1921	0	0	0
T3	223188	1241	0	0
T4	5152	142	0	0
T5	1118	0	0	0
T6	258835	483	0	0
T7	172521	1413	0	0
T8	453209	0	0	0
T9	60845	0	0	0
T10	68913	0	0	0
T11	0	294	0	0
T28	0	480	0	0
T30	0	4877	0	0
T31	0	814	0	0
T40	0	307	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	458253414	0	0
T1	193573	193504	0	0
T2	1921	1828	0	0
T3	223188	223182	0	0
T4	5152	5100	0	0
T5	1118	1036	0	0
T6	258835	258746	0	0
T7	172521	172460	0	0
T8	453209	453155	0	0
T9	60845	60774	0	0
T10	68913	68813	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	458253414	0	0
T1	193573	193504	0	0
T2	1921	1828	0	0
T3	223188	223182	0	0
T4	5152	5100	0	0
T5	1118	1036	0	0
T6	258835	258746	0	0
T7	172521	172460	0	0
T8	453209	453155	0	0
T9	60845	60774	0	0
T10	68913	68813	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	458253414	0	0
T1	193573	193504	0	0
T2	1921	1828	0	0
T3	223188	223182	0	0
T4	5152	5100	0	0
T5	1118	1036	0	0
T6	258835	258746	0	0
T7	172521	172460	0	0
T8	453209	453155	0	0
T9	60845	60774	0	0
T10	68913	68813	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	458380983	6180513	0	0
DepthKnown_A	458380983	458253414	0	0
RvalidKnown_A	458380983	458253414	0	0
WreadyKnown_A	458380983	458253414	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	6180513	0	0
T1	193573	786	0	0
T2	1921	79	0	0
T3	223188	4085	0	0
T4	5152	209	0	0
T5	1118	79	0	0
T6	258835	1832	0	0
T7	172521	902	0	0
T8	453209	19380	0	0
T9	60845	1798	0	0
T10	68913	3741	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	458253414	0	0
T1	193573	193504	0	0
T2	1921	1828	0	0
T3	223188	223182	0	0
T4	5152	5100	0	0
T5	1118	1036	0	0
T6	258835	258746	0	0
T7	172521	172460	0	0
T8	453209	453155	0	0
T9	60845	60774	0	0
T10	68913	68813	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	458253414	0	0
T1	193573	193504	0	0
T2	1921	1828	0	0
T3	223188	223182	0	0
T4	5152	5100	0	0
T5	1118	1036	0	0
T6	258835	258746	0	0
T7	172521	172460	0	0
T8	453209	453155	0	0
T9	60845	60774	0	0
T10	68913	68813	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	458253414	0	0
T1	193573	193504	0	0
T2	1921	1828	0	0
T3	223188	223182	0	0
T4	5152	5100	0	0
T5	1118	1036	0	0
T6	258835	258746	0	0
T7	172521	172460	0	0
T8	453209	453155	0	0
T9	60845	60774	0	0
T10	68913	68813	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	458380983	13762104	0	0
DepthKnown_A	458380983	458253414	0	0
RvalidKnown_A	458380983	458253414	0	0
WreadyKnown_A	458380983	458253414	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	13762104	0	0
T1	193573	786	0	0
T2	1921	79	0	0
T3	223188	17670	0	0
T4	5152	603	0	0
T5	1118	79	0	0
T6	258835	1829	0	0
T7	172521	2816	0	0
T8	453209	59284	0	0
T9	60845	7681	0	0
T10	68913	3741	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	458253414	0	0
T1	193573	193504	0	0
T2	1921	1828	0	0
T3	223188	223182	0	0
T4	5152	5100	0	0
T5	1118	1036	0	0
T6	258835	258746	0	0
T7	172521	172460	0	0
T8	453209	453155	0	0
T9	60845	60774	0	0
T10	68913	68813	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	458253414	0	0
T1	193573	193504	0	0
T2	1921	1828	0	0
T3	223188	223182	0	0
T4	5152	5100	0	0
T5	1118	1036	0	0
T6	258835	258746	0	0
T7	172521	172460	0	0
T8	453209	453155	0	0
T9	60845	60774	0	0
T10	68913	68813	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	458253414	0	0
T1	193573	193504	0	0
T2	1921	1828	0	0
T3	223188	223182	0	0
T4	5152	5100	0	0
T5	1118	1036	0	0
T6	258835	258746	0	0
T7	172521	172460	0	0
T8	453209	453155	0	0
T9	60845	60774	0	0
T10	68913	68813	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0