Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T30,T31
1	0	Covered	T4,T30,T31

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T29,T22
1	0	Unreachable
1	1	Covered	T4,T30,T31

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Unreachable
1	1	Covered	T1,T3,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	750341787	601730779	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	750341787	3705437	0	0
GntImpliesValid_A	750341787	3705437	0	0
GrantKnown_A	750341787	601730779	0	0
IdxKnown_A	750341787	601730779	0	0
IndexIsCorrect_A	750341787	3705437	0	0
LockArbDecision_A	750341787	0	0	0
NoReadyValidNoGrant_A	750341787	0	0	0
ReadyAndValidImplyGrant_A	750341787	3705437	0	0
ReqAndReadyImplyGrant_A	750341787	3705437	0	0
ReqImpliesValid_A	750341787	3705437	0	0
ReqStaysHighUntilGranted0_M	750341787	0	0	0
RoundRobin_A	750341787	3	0	956
ValidKnown_A	750341787	601730779	0	0
gen_data_port_assertion.DataFlow_A	750341787	3705437	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750341787	601730779	0	0
T1	356010	354542	0	0
T2	1921	1828	0	0
T3	650442	648232	0	0
T4	18366	11404	0	0
T5	1118	1036	0	0
T6	1206693	729077	0	0
T7	842037	505717	0	0
T8	564571	508697	0	0
T9	85933	73318	0	0
T10	101777	85245	0	0
T11	398750	198834	0	0
T12	33072	16536	0	0
T13	75978	0	0	0
T22	0	216	0	0
T23	0	360	0	0
T29	216	216	0	0
T30	0	34664	0	0
T31	0	448216	0	0
T32	0	39760	0	0
T33	0	108832	0	0
T34	0	80736	0	0
T35	0	315016	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750341787	3705437	0	0
T1	356010	4492	0	0
T2	1921	0	0	0
T3	650442	17632	0	0
T4	18366	354	0	0
T5	1118	0	0	0
T6	1206693	16803	0	0
T7	842037	10288	0	0
T8	564571	832	0	0
T9	85933	832	0	0
T10	101777	832	0	0
T11	398750	2830	0	0
T12	33072	832	0	0
T13	75978	0	0	0
T17	0	2299	0	0
T28	0	9346	0	0
T29	216	0	0	0
T30	0	17264	0	0
T31	0	4840	0	0
T33	0	1841	0	0
T35	0	5456	0	0
T40	0	1534	0	0
T43	0	873	0	0
T47	0	5342	0	0
T50	0	4457	0	0
T51	0	432	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750341787	3705437	0	0
T1	356010	4492	0	0
T2	1921	0	0	0
T3	650442	17632	0	0
T4	18366	354	0	0
T5	1118	0	0	0
T6	1206693	16803	0	0
T7	842037	10288	0	0
T8	564571	832	0	0
T9	85933	832	0	0
T10	101777	832	0	0
T11	398750	2830	0	0
T12	33072	832	0	0
T13	75978	0	0	0
T17	0	2299	0	0
T28	0	9346	0	0
T29	216	0	0	0
T30	0	17264	0	0
T31	0	4840	0	0
T33	0	1841	0	0
T35	0	5456	0	0
T40	0	1534	0	0
T43	0	873	0	0
T47	0	5342	0	0
T50	0	4457	0	0
T51	0	432	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750341787	601730779	0	0
T1	356010	354542	0	0
T2	1921	1828	0	0
T3	650442	648232	0	0
T4	18366	11404	0	0
T5	1118	1036	0	0
T6	1206693	729077	0	0
T7	842037	505717	0	0
T8	564571	508697	0	0
T9	85933	73318	0	0
T10	101777	85245	0	0
T11	398750	198834	0	0
T12	33072	16536	0	0
T13	75978	0	0	0
T22	0	216	0	0
T23	0	360	0	0
T29	216	216	0	0
T30	0	34664	0	0
T31	0	448216	0	0
T32	0	39760	0	0
T33	0	108832	0	0
T34	0	80736	0	0
T35	0	315016	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750341787	601730779	0	0
T1	356010	354542	0	0
T2	1921	1828	0	0
T3	650442	648232	0	0
T4	18366	11404	0	0
T5	1118	1036	0	0
T6	1206693	729077	0	0
T7	842037	505717	0	0
T8	564571	508697	0	0
T9	85933	73318	0	0
T10	101777	85245	0	0
T11	398750	198834	0	0
T12	33072	16536	0	0
T13	75978	0	0	0
T22	0	216	0	0
T23	0	360	0	0
T29	216	216	0	0
T30	0	34664	0	0
T31	0	448216	0	0
T32	0	39760	0	0
T33	0	108832	0	0
T34	0	80736	0	0
T35	0	315016	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750341787	3705437	0	0
T1	356010	4492	0	0
T2	1921	0	0	0
T3	650442	17632	0	0
T4	18366	354	0	0
T5	1118	0	0	0
T6	1206693	16803	0	0
T7	842037	10288	0	0
T8	564571	832	0	0
T9	85933	832	0	0
T10	101777	832	0	0
T11	398750	2830	0	0
T12	33072	832	0	0
T13	75978	0	0	0
T17	0	2299	0	0
T28	0	9346	0	0
T29	216	0	0	0
T30	0	17264	0	0
T31	0	4840	0	0
T33	0	1841	0	0
T35	0	5456	0	0
T40	0	1534	0	0
T43	0	873	0	0
T47	0	5342	0	0
T50	0	4457	0	0
T51	0	432	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750341787	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750341787	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750341787	3705437	0	0
T1	356010	4492	0	0
T2	1921	0	0	0
T3	650442	17632	0	0
T4	18366	354	0	0
T5	1118	0	0	0
T6	1206693	16803	0	0
T7	842037	10288	0	0
T8	564571	832	0	0
T9	85933	832	0	0
T10	101777	832	0	0
T11	398750	2830	0	0
T12	33072	832	0	0
T13	75978	0	0	0
T17	0	2299	0	0
T28	0	9346	0	0
T29	216	0	0	0
T30	0	17264	0	0
T31	0	4840	0	0
T33	0	1841	0	0
T35	0	5456	0	0
T40	0	1534	0	0
T43	0	873	0	0
T47	0	5342	0	0
T50	0	4457	0	0
T51	0	432	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750341787	3705437	0	0
T1	356010	4492	0	0
T2	1921	0	0	0
T3	650442	17632	0	0
T4	18366	354	0	0
T5	1118	0	0	0
T6	1206693	16803	0	0
T7	842037	10288	0	0
T8	564571	832	0	0
T9	85933	832	0	0
T10	101777	832	0	0
T11	398750	2830	0	0
T12	33072	832	0	0
T13	75978	0	0	0
T17	0	2299	0	0
T28	0	9346	0	0
T29	216	0	0	0
T30	0	17264	0	0
T31	0	4840	0	0
T33	0	1841	0	0
T35	0	5456	0	0
T40	0	1534	0	0
T43	0	873	0	0
T47	0	5342	0	0
T50	0	4457	0	0
T51	0	432	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750341787	3705437	0	0
T1	356010	4492	0	0
T2	1921	0	0	0
T3	650442	17632	0	0
T4	18366	354	0	0
T5	1118	0	0	0
T6	1206693	16803	0	0
T7	842037	10288	0	0
T8	564571	832	0	0
T9	85933	832	0	0
T10	101777	832	0	0
T11	398750	2830	0	0
T12	33072	832	0	0
T13	75978	0	0	0
T17	0	2299	0	0
T28	0	9346	0	0
T29	216	0	0	0
T30	0	17264	0	0
T31	0	4840	0	0
T33	0	1841	0	0
T35	0	5456	0	0
T40	0	1534	0	0
T43	0	873	0	0
T47	0	5342	0	0
T50	0	4457	0	0
T51	0	432	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	750341787	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750341787	3	0	956
T52	769264	1	0	1
T53	0	1	0	0
T54	0	1	0	0
T55	294533	0	0	1
T56	25496	0	0	1
T57	1183	0	0	1
T58	1841	0	0	1
T59	47384	0	0	1
T60	295202	0	0	1
T61	176322	0	0	1
T62	876326	0	0	1
T63	472116	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750341787	601730779	0	0
T1	356010	354542	0	0
T2	1921	1828	0	0
T3	650442	648232	0	0
T4	18366	11404	0	0
T5	1118	1036	0	0
T6	1206693	729077	0	0
T7	842037	505717	0	0
T8	564571	508697	0	0
T9	85933	73318	0	0
T10	101777	85245	0	0
T11	398750	198834	0	0
T12	33072	16536	0	0
T13	75978	0	0	0
T22	0	216	0	0
T23	0	360	0	0
T29	216	216	0	0
T30	0	34664	0	0
T31	0	448216	0	0
T32	0	39760	0	0
T33	0	108832	0	0
T34	0	80736	0	0
T35	0	315016	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750341787	3705437	0	0
T1	356010	4492	0	0
T2	1921	0	0	0
T3	650442	17632	0	0
T4	18366	354	0	0
T5	1118	0	0	0
T6	1206693	16803	0	0
T7	842037	10288	0	0
T8	564571	832	0	0
T9	85933	832	0	0
T10	101777	832	0	0
T11	398750	2830	0	0
T12	33072	832	0	0
T13	75978	0	0	0
T17	0	2299	0	0
T28	0	9346	0	0
T29	216	0	0	0
T30	0	17264	0	0
T31	0	4840	0	0
T33	0	1841	0	0
T35	0	5456	0	0
T40	0	1534	0	0
T43	0	873	0	0
T47	0	5342	0	0
T50	0	4457	0	0
T51	0	432	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T30,T31
1	0	Covered	T4,T30,T31

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T29,T22
1	0	Unreachable
1	1	Covered	T4,T30,T31

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T30,T31
0	0	1	Unreachable
0	0	0	Covered	T4,T29,T22

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T30,T31
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T30,T31
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	147200904	28902872	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	147200904	651878	0	0
GntImpliesValid_A	147200904	651878	0	0
GrantKnown_A	147200904	28902872	0	0
IdxKnown_A	147200904	28902872	0	0
IndexIsCorrect_A	147200904	651878	0	0
LockArbDecision_A	147200904	0	0	0
NoReadyValidNoGrant_A	147200904	0	0	0
ReadyAndValidImplyGrant_A	147200904	651878	0	0
ReqAndReadyImplyGrant_A	147200904	651878	0	0
ReqImpliesValid_A	147200904	651878	0	0
ReqStaysHighUntilGranted0_M	147200904	0	0	0
RoundRobin_A	147200904	0	0	0
ValidKnown_A	147200904	28902872	0	0
gen_data_port_assertion.DataFlow_A	147200904	651878	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	28902872	0	0
T4	6607	6304	0	0
T6	473929	0	0	0
T7	334758	0	0	0
T8	55681	0	0	0
T9	12544	0	0	0
T10	16432	0	0	0
T11	199375	0	0	0
T12	16536	0	0	0
T13	75978	0	0	0
T22	0	216	0	0
T23	0	360	0	0
T29	216	216	0	0
T30	0	34664	0	0
T31	0	448216	0	0
T32	0	39760	0	0
T33	0	108832	0	0
T34	0	80736	0	0
T35	0	315016	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	651878	0	0
T4	6607	246	0	0
T6	473929	0	0	0
T7	334758	0	0	0
T8	55681	0	0	0
T9	12544	0	0	0
T10	16432	0	0	0
T11	199375	0	0	0
T12	16536	0	0	0
T13	75978	0	0	0
T17	0	2299	0	0
T29	216	0	0	0
T30	0	1533	0	0
T31	0	4578	0	0
T33	0	1841	0	0
T35	0	5456	0	0
T43	0	873	0	0
T47	0	5342	0	0
T50	0	4457	0	0
T51	0	432	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	651878	0	0
T4	6607	246	0	0
T6	473929	0	0	0
T7	334758	0	0	0
T8	55681	0	0	0
T9	12544	0	0	0
T10	16432	0	0	0
T11	199375	0	0	0
T12	16536	0	0	0
T13	75978	0	0	0
T17	0	2299	0	0
T29	216	0	0	0
T30	0	1533	0	0
T31	0	4578	0	0
T33	0	1841	0	0
T35	0	5456	0	0
T43	0	873	0	0
T47	0	5342	0	0
T50	0	4457	0	0
T51	0	432	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	28902872	0	0
T4	6607	6304	0	0
T6	473929	0	0	0
T7	334758	0	0	0
T8	55681	0	0	0
T9	12544	0	0	0
T10	16432	0	0	0
T11	199375	0	0	0
T12	16536	0	0	0
T13	75978	0	0	0
T22	0	216	0	0
T23	0	360	0	0
T29	216	216	0	0
T30	0	34664	0	0
T31	0	448216	0	0
T32	0	39760	0	0
T33	0	108832	0	0
T34	0	80736	0	0
T35	0	315016	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	28902872	0	0
T4	6607	6304	0	0
T6	473929	0	0	0
T7	334758	0	0	0
T8	55681	0	0	0
T9	12544	0	0	0
T10	16432	0	0	0
T11	199375	0	0	0
T12	16536	0	0	0
T13	75978	0	0	0
T22	0	216	0	0
T23	0	360	0	0
T29	216	216	0	0
T30	0	34664	0	0
T31	0	448216	0	0
T32	0	39760	0	0
T33	0	108832	0	0
T34	0	80736	0	0
T35	0	315016	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	651878	0	0
T4	6607	246	0	0
T6	473929	0	0	0
T7	334758	0	0	0
T8	55681	0	0	0
T9	12544	0	0	0
T10	16432	0	0	0
T11	199375	0	0	0
T12	16536	0	0	0
T13	75978	0	0	0
T17	0	2299	0	0
T29	216	0	0	0
T30	0	1533	0	0
T31	0	4578	0	0
T33	0	1841	0	0
T35	0	5456	0	0
T43	0	873	0	0
T47	0	5342	0	0
T50	0	4457	0	0
T51	0	432	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	651878	0	0
T4	6607	246	0	0
T6	473929	0	0	0
T7	334758	0	0	0
T8	55681	0	0	0
T9	12544	0	0	0
T10	16432	0	0	0
T11	199375	0	0	0
T12	16536	0	0	0
T13	75978	0	0	0
T17	0	2299	0	0
T29	216	0	0	0
T30	0	1533	0	0
T31	0	4578	0	0
T33	0	1841	0	0
T35	0	5456	0	0
T43	0	873	0	0
T47	0	5342	0	0
T50	0	4457	0	0
T51	0	432	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	651878	0	0
T4	6607	246	0	0
T6	473929	0	0	0
T7	334758	0	0	0
T8	55681	0	0	0
T9	12544	0	0	0
T10	16432	0	0	0
T11	199375	0	0	0
T12	16536	0	0	0
T13	75978	0	0	0
T17	0	2299	0	0
T29	216	0	0	0
T30	0	1533	0	0
T31	0	4578	0	0
T33	0	1841	0	0
T35	0	5456	0	0
T43	0	873	0	0
T47	0	5342	0	0
T50	0	4457	0	0
T51	0	432	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	651878	0	0
T4	6607	246	0	0
T6	473929	0	0	0
T7	334758	0	0	0
T8	55681	0	0	0
T9	12544	0	0	0
T10	16432	0	0	0
T11	199375	0	0	0
T12	16536	0	0	0
T13	75978	0	0	0
T17	0	2299	0	0
T29	216	0	0	0
T30	0	1533	0	0
T31	0	4578	0	0
T33	0	1841	0	0
T35	0	5456	0	0
T43	0	873	0	0
T47	0	5342	0	0
T50	0	4457	0	0
T51	0	432	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	28902872	0	0
T4	6607	6304	0	0
T6	473929	0	0	0
T7	334758	0	0	0
T8	55681	0	0	0
T9	12544	0	0	0
T10	16432	0	0	0
T11	199375	0	0	0
T12	16536	0	0	0
T13	75978	0	0	0
T22	0	216	0	0
T23	0	360	0	0
T29	216	216	0	0
T30	0	34664	0	0
T31	0	448216	0	0
T32	0	39760	0	0
T33	0	108832	0	0
T34	0	80736	0	0
T35	0	315016	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	651878	0	0
T4	6607	246	0	0
T6	473929	0	0	0
T7	334758	0	0	0
T8	55681	0	0	0
T9	12544	0	0	0
T10	16432	0	0	0
T11	199375	0	0	0
T12	16536	0	0	0
T13	75978	0	0	0
T17	0	2299	0	0
T29	216	0	0	0
T30	0	1533	0	0
T31	0	4578	0	0
T33	0	1841	0	0
T35	0	5456	0	0
T43	0	873	0	0
T47	0	5342	0	0
T50	0	4457	0	0
T51	0	432	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Unreachable
1	1	Covered	T1,T3,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	147200904	116974087	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	147200904	804962	0	0
GntImpliesValid_A	147200904	804962	0	0
GrantKnown_A	147200904	116974087	0	0
IdxKnown_A	147200904	116974087	0	0
IndexIsCorrect_A	147200904	804962	0	0
LockArbDecision_A	147200904	0	0	0
NoReadyValidNoGrant_A	147200904	0	0	0
ReadyAndValidImplyGrant_A	147200904	804962	0	0
ReqAndReadyImplyGrant_A	147200904	804962	0	0
ReqImpliesValid_A	147200904	804962	0	0
ReqStaysHighUntilGranted0_M	147200904	0	0	0
RoundRobin_A	147200904	0	0	0
ValidKnown_A	147200904	116974087	0	0
gen_data_port_assertion.DataFlow_A	147200904	804962	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	116974087	0	0
T1	162437	161038	0	0
T3	427254	425050	0	0
T4	6607	0	0	0
T6	473929	470331	0	0
T7	334758	333257	0	0
T8	55681	55542	0	0
T9	12544	12544	0	0
T10	16432	16432	0	0
T11	199375	198834	0	0
T12	16536	16536	0	0
T13	0	75978	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	804962	0	0
T1	162437	262	0	0
T3	427254	7336	0	0
T4	6607	0	0	0
T6	473929	4641	0	0
T7	334758	2288	0	0
T8	55681	0	0	0
T9	12544	0	0	0
T10	16432	0	0	0
T11	199375	263	0	0
T12	16536	0	0	0
T28	0	9346	0	0
T30	0	15731	0	0
T31	0	262	0	0
T40	0	1534	0	0
T64	0	257	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	804962	0	0
T1	162437	262	0	0
T3	427254	7336	0	0
T4	6607	0	0	0
T6	473929	4641	0	0
T7	334758	2288	0	0
T8	55681	0	0	0
T9	12544	0	0	0
T10	16432	0	0	0
T11	199375	263	0	0
T12	16536	0	0	0
T28	0	9346	0	0
T30	0	15731	0	0
T31	0	262	0	0
T40	0	1534	0	0
T64	0	257	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	116974087	0	0
T1	162437	161038	0	0
T3	427254	425050	0	0
T4	6607	0	0	0
T6	473929	470331	0	0
T7	334758	333257	0	0
T8	55681	55542	0	0
T9	12544	12544	0	0
T10	16432	16432	0	0
T11	199375	198834	0	0
T12	16536	16536	0	0
T13	0	75978	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	116974087	0	0
T1	162437	161038	0	0
T3	427254	425050	0	0
T4	6607	0	0	0
T6	473929	470331	0	0
T7	334758	333257	0	0
T8	55681	55542	0	0
T9	12544	12544	0	0
T10	16432	16432	0	0
T11	199375	198834	0	0
T12	16536	16536	0	0
T13	0	75978	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	804962	0	0
T1	162437	262	0	0
T3	427254	7336	0	0
T4	6607	0	0	0
T6	473929	4641	0	0
T7	334758	2288	0	0
T8	55681	0	0	0
T9	12544	0	0	0
T10	16432	0	0	0
T11	199375	263	0	0
T12	16536	0	0	0
T28	0	9346	0	0
T30	0	15731	0	0
T31	0	262	0	0
T40	0	1534	0	0
T64	0	257	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	804962	0	0
T1	162437	262	0	0
T3	427254	7336	0	0
T4	6607	0	0	0
T6	473929	4641	0	0
T7	334758	2288	0	0
T8	55681	0	0	0
T9	12544	0	0	0
T10	16432	0	0	0
T11	199375	263	0	0
T12	16536	0	0	0
T28	0	9346	0	0
T30	0	15731	0	0
T31	0	262	0	0
T40	0	1534	0	0
T64	0	257	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	804962	0	0
T1	162437	262	0	0
T3	427254	7336	0	0
T4	6607	0	0	0
T6	473929	4641	0	0
T7	334758	2288	0	0
T8	55681	0	0	0
T9	12544	0	0	0
T10	16432	0	0	0
T11	199375	263	0	0
T12	16536	0	0	0
T28	0	9346	0	0
T30	0	15731	0	0
T31	0	262	0	0
T40	0	1534	0	0
T64	0	257	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	804962	0	0
T1	162437	262	0	0
T3	427254	7336	0	0
T4	6607	0	0	0
T6	473929	4641	0	0
T7	334758	2288	0	0
T8	55681	0	0	0
T9	12544	0	0	0
T10	16432	0	0	0
T11	199375	263	0	0
T12	16536	0	0	0
T28	0	9346	0	0
T30	0	15731	0	0
T31	0	262	0	0
T40	0	1534	0	0
T64	0	257	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	116974087	0	0
T1	162437	161038	0	0
T3	427254	425050	0	0
T4	6607	0	0	0
T6	473929	470331	0	0
T7	334758	333257	0	0
T8	55681	55542	0	0
T9	12544	12544	0	0
T10	16432	16432	0	0
T11	199375	198834	0	0
T12	16536	16536	0	0
T13	0	75978	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147200904	804962	0	0
T1	162437	262	0	0
T3	427254	7336	0	0
T4	6607	0	0	0
T6	473929	4641	0	0
T7	334758	2288	0	0
T8	55681	0	0	0
T9	12544	0	0	0
T10	16432	0	0	0
T11	199375	263	0	0
T12	16536	0	0	0
T28	0	9346	0	0
T30	0	15731	0	0
T31	0	262	0	0
T40	0	1534	0	0
T64	0	257	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455939979	455853820	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	455939979	2248597	0	0
GntImpliesValid_A	455939979	2248597	0	0
GrantKnown_A	455939979	455853820	0	0
IdxKnown_A	455939979	455853820	0	0
IndexIsCorrect_A	455939979	2248597	0	0
LockArbDecision_A	455939979	0	0	0
NoReadyValidNoGrant_A	455939979	0	0	0
ReadyAndValidImplyGrant_A	455939979	2248597	0	0
ReqAndReadyImplyGrant_A	455939979	2248597	0	0
ReqImpliesValid_A	455939979	2248597	0	0
ReqStaysHighUntilGranted0_M	455939979	0	0	0
RoundRobin_A	455939979	3	0	956
ValidKnown_A	455939979	455853820	0	0
gen_data_port_assertion.DataFlow_A	455939979	2248597	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455939979	455853820	0	0
T1	193573	193504	0	0
T2	1921	1828	0	0
T3	223188	223182	0	0
T4	5152	5100	0	0
T5	1118	1036	0	0
T6	258835	258746	0	0
T7	172521	172460	0	0
T8	453209	453155	0	0
T9	60845	60774	0	0
T10	68913	68813	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455939979	2248597	0	0
T1	193573	4230	0	0
T2	1921	0	0	0
T3	223188	10296	0	0
T4	5152	108	0	0
T5	1118	0	0	0
T6	258835	12162	0	0
T7	172521	8000	0	0
T8	453209	832	0	0
T9	60845	832	0	0
T10	68913	832	0	0
T11	0	2567	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455939979	2248597	0	0
T1	193573	4230	0	0
T2	1921	0	0	0
T3	223188	10296	0	0
T4	5152	108	0	0
T5	1118	0	0	0
T6	258835	12162	0	0
T7	172521	8000	0	0
T8	453209	832	0	0
T9	60845	832	0	0
T10	68913	832	0	0
T11	0	2567	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455939979	455853820	0	0
T1	193573	193504	0	0
T2	1921	1828	0	0
T3	223188	223182	0	0
T4	5152	5100	0	0
T5	1118	1036	0	0
T6	258835	258746	0	0
T7	172521	172460	0	0
T8	453209	453155	0	0
T9	60845	60774	0	0
T10	68913	68813	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455939979	455853820	0	0
T1	193573	193504	0	0
T2	1921	1828	0	0
T3	223188	223182	0	0
T4	5152	5100	0	0
T5	1118	1036	0	0
T6	258835	258746	0	0
T7	172521	172460	0	0
T8	453209	453155	0	0
T9	60845	60774	0	0
T10	68913	68813	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455939979	2248597	0	0
T1	193573	4230	0	0
T2	1921	0	0	0
T3	223188	10296	0	0
T4	5152	108	0	0
T5	1118	0	0	0
T6	258835	12162	0	0
T7	172521	8000	0	0
T8	453209	832	0	0
T9	60845	832	0	0
T10	68913	832	0	0
T11	0	2567	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455939979	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455939979	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455939979	2248597	0	0
T1	193573	4230	0	0
T2	1921	0	0	0
T3	223188	10296	0	0
T4	5152	108	0	0
T5	1118	0	0	0
T6	258835	12162	0	0
T7	172521	8000	0	0
T8	453209	832	0	0
T9	60845	832	0	0
T10	68913	832	0	0
T11	0	2567	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455939979	2248597	0	0
T1	193573	4230	0	0
T2	1921	0	0	0
T3	223188	10296	0	0
T4	5152	108	0	0
T5	1118	0	0	0
T6	258835	12162	0	0
T7	172521	8000	0	0
T8	453209	832	0	0
T9	60845	832	0	0
T10	68913	832	0	0
T11	0	2567	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455939979	2248597	0	0
T1	193573	4230	0	0
T2	1921	0	0	0
T3	223188	10296	0	0
T4	5152	108	0	0
T5	1118	0	0	0
T6	258835	12162	0	0
T7	172521	8000	0	0
T8	453209	832	0	0
T9	60845	832	0	0
T10	68913	832	0	0
T11	0	2567	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455939979	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455939979	3	0	956
T52	769264	1	0	1
T53	0	1	0	0
T54	0	1	0	0
T55	294533	0	0	1
T56	25496	0	0	1
T57	1183	0	0	1
T58	1841	0	0	1
T59	47384	0	0	1
T60	295202	0	0	1
T61	176322	0	0	1
T62	876326	0	0	1
T63	472116	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455939979	455853820	0	0
T1	193573	193504	0	0
T2	1921	1828	0	0
T3	223188	223182	0	0
T4	5152	5100	0	0
T5	1118	1036	0	0
T6	258835	258746	0	0
T7	172521	172460	0	0
T8	453209	453155	0	0
T9	60845	60774	0	0
T10	68913	68813	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455939979	2248597	0	0
T1	193573	4230	0	0
T2	1921	0	0	0
T3	223188	10296	0	0
T4	5152	108	0	0
T5	1118	0	0	0
T6	258835	12162	0	0
T7	172521	8000	0	0
T8	453209	832	0	0
T9	60845	832	0	0
T10	68913	832	0	0
T11	0	2567	0	0
T12	0	832	0	0