Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	458380983	2647	0	0
addr_swap_data_rd_A	458380983	2069	0	0
addr_swap_mask_rd_A	458380983	1990	0	0
cfg_rd_A	458380983	2610	0	0
cmd_filter_0_rd_A	458380983	7461	0	0
cmd_filter_1_rd_A	458380983	8891	0	0
cmd_filter_2_rd_A	458380983	7414	0	0
cmd_filter_3_rd_A	458380983	8858	0	0
cmd_filter_4_rd_A	458380983	7834	0	0
cmd_filter_5_rd_A	458380983	8828	0	0
cmd_filter_6_rd_A	458380983	8162	0	0
cmd_filter_7_rd_A	458380983	7390	0	0
cmd_info_0_rd_A	458380983	4545	0	0
cmd_info_10_rd_A	458380983	4712	0	0
cmd_info_11_rd_A	458380983	4503	0	0
cmd_info_12_rd_A	458380983	4762	0	0
cmd_info_13_rd_A	458380983	4845	0	0
cmd_info_14_rd_A	458380983	4574	0	0
cmd_info_15_rd_A	458380983	4390	0	0
cmd_info_16_rd_A	458380983	4666	0	0
cmd_info_17_rd_A	458380983	4666	0	0
cmd_info_18_rd_A	458380983	4454	0	0
cmd_info_19_rd_A	458380983	4839	0	0
cmd_info_1_rd_A	458380983	4727	0	0
cmd_info_20_rd_A	458380983	4385	0	0
cmd_info_21_rd_A	458380983	4652	0	0
cmd_info_22_rd_A	458380983	4262	0	0
cmd_info_23_rd_A	458380983	4743	0	0
cmd_info_2_rd_A	458380983	4539	0	0
cmd_info_3_rd_A	458380983	4491	0	0
cmd_info_4_rd_A	458380983	4568	0	0
cmd_info_5_rd_A	458380983	4277	0	0
cmd_info_6_rd_A	458380983	4748	0	0
cmd_info_7_rd_A	458380983	4508	0	0
cmd_info_8_rd_A	458380983	4550	0	0
cmd_info_9_rd_A	458380983	4242	0	0
cmd_info_en4b_rd_A	458380983	2391	0	0
cmd_info_ex4b_rd_A	458380983	2435	0	0
cmd_info_wrdi_rd_A	458380983	2369	0	0
cmd_info_wren_rd_A	458380983	2196	0	0
intercept_en_rd_A	458380983	2853	0	0
intr_enable_rd_A	458380983	4598	0	0
jedec_cc_rd_A	458380983	2373	0	0
jedec_id_rd_A	458380983	2368	0	0
mailbox_addr_rd_A	458380983	2067	0	0
payload_swap_data_rd_A	458380983	2068	0	0
payload_swap_mask_rd_A	458380983	2051	0	0
read_threshold_rd_A	458380983	2175	0	0
tpm_access_0_rd_A	458380983	2590	0	0
tpm_access_1_rd_A	458380983	2111	0	0
tpm_cfg_rd_A	458380983	3187	0	0
tpm_did_vid_rd_A	458380983	2420	0	0
tpm_int_enable_rd_A	458380983	2108	0	0
tpm_int_status_rd_A	458380983	2114	0	0
tpm_int_vector_rd_A	458380983	2092	0	0
tpm_intf_capability_rd_A	458380983	2150	0	0
tpm_rid_rd_A	458380983	2120	0	0
tpm_sts_rd_A	458380983	2119	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2647	0	0
T69	57773	2	0	0
T70	11570	1	0	0
T71	33765	2	0	0
T90	1780	34	0	0
T91	8592	7	0	0
T92	4018	169	0	0
T93	18618	278	0	0
T103	5277	11	0	0
T106	5580	23	0	0
T114	2222	4	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2069	0	0
T70	11570	18	0	0
T71	33765	37	0	0
T116	9861	15	0	0
T117	3438	1	0	0
T119	1941	4	0	0
T120	6481	1	0	0
T156	19847	84	0	0
T157	7481	7	0	0
T158	7362	26	0	0
T159	21417	95	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	1990	0	0
T70	11570	4	0	0
T71	33765	38	0	0
T116	9861	16	0	0
T119	1941	7	0	0
T120	6481	12	0	0
T121	270748	644	0	0
T156	19847	34	0	0
T157	7481	11	0	0
T158	7362	10	0	0
T159	21417	53	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2610	0	0
T70	11570	29	0	0
T71	33765	84	0	0
T116	9861	15	0	0
T120	6481	34	0	0
T121	270748	659	0	0
T156	19847	75	0	0
T157	7481	10	0	0
T158	7362	39	0	0
T159	21417	116	0	0
T160	11246	39	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	7461	0	0
T70	11570	138	0	0
T71	33765	163	0	0
T116	9861	95	0	0
T119	1941	3	0	0
T120	6481	144	0	0
T121	270748	686	0	0
T156	19847	34	0	0
T157	7481	12	0	0
T158	7362	16	0	0
T159	21417	58	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	8891	0	0
T70	11570	236	0	0
T71	33765	541	0	0
T113	9329	8	0	0
T116	9861	235	0	0
T120	6481	160	0	0
T121	270748	610	0	0
T156	19847	44	0	0
T157	7481	36	0	0
T159	21417	71	0	0
T160	11246	93	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	7414	0	0
T70	11570	121	0	0
T71	33765	266	0	0
T116	9861	168	0	0
T117	3438	81	0	0
T119	1941	3	0	0
T120	6481	7	0	0
T121	270748	684	0	0
T156	19847	74	0	0
T158	7362	24	0	0
T159	21417	51	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	8858	0	0
T70	11570	110	0	0
T71	33765	395	0	0
T116	9861	137	0	0
T119	1941	8	0	0
T120	6481	126	0	0
T121	270748	713	0	0
T156	19847	45	0	0
T157	7481	35	0	0
T158	7362	13	0	0
T159	21417	33	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	7834	0	0
T70	11570	19	0	0
T71	33765	412	0	0
T116	9861	11	0	0
T117	3438	2	0	0
T120	6481	112	0	0
T121	270748	692	0	0
T156	19847	20	0	0
T157	7481	8	0	0
T158	7362	26	0	0
T159	21417	15	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	8828	0	0
T70	11570	246	0	0
T71	33765	918	0	0
T116	9861	248	0	0
T120	6481	173	0	0
T121	270748	637	0	0
T156	19847	68	0	0
T157	7481	4	0	0
T158	7362	33	0	0
T159	21417	103	0	0
T160	11246	8	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	8162	0	0
T70	11570	20	0	0
T71	33765	468	0	0
T116	9861	290	0	0
T117	3438	35	0	0
T120	6481	3	0	0
T121	270748	651	0	0
T156	19847	92	0	0
T157	7481	15	0	0
T158	7362	5	0	0
T159	21417	81	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	7390	0	0
T70	11570	15	0	0
T71	33765	826	0	0
T116	9861	162	0	0
T120	6481	3	0	0
T121	270748	673	0	0
T156	19847	71	0	0
T157	7481	35	0	0
T158	7362	12	0	0
T159	21417	77	0	0
T160	11246	384	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4545	0	0
T70	11570	27	0	0
T71	33765	235	0	0
T116	9861	49	0	0
T117	3438	17	0	0
T119	1941	2	0	0
T120	6481	113	0	0
T156	19847	84	0	0
T157	7481	19	0	0
T158	7362	13	0	0
T159	21417	9	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4712	0	0
T70	11570	119	0	0
T71	33765	282	0	0
T116	9861	64	0	0
T117	3438	17	0	0
T119	1941	6	0	0
T120	6481	13	0	0
T156	19847	73	0	0
T157	7481	18	0	0
T158	7362	35	0	0
T159	21417	60	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4503	0	0
T70	11570	68	0	0
T71	33765	310	0	0
T116	9861	58	0	0
T117	3438	24	0	0
T119	1941	7	0	0
T120	6481	34	0	0
T156	19847	68	0	0
T157	7481	12	0	0
T158	7362	12	0	0
T159	21417	47	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4762	0	0
T70	11570	143	0	0
T71	33765	224	0	0
T116	9861	6	0	0
T119	1941	3	0	0
T120	6481	53	0	0
T121	270748	702	0	0
T156	19847	96	0	0
T157	7481	10	0	0
T158	7362	29	0	0
T159	21417	73	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4845	0	0
T70	11570	106	0	0
T71	33765	274	0	0
T116	9861	81	0	0
T117	3438	17	0	0
T119	1941	9	0	0
T120	6481	8	0	0
T156	19847	124	0	0
T157	7481	32	0	0
T158	7362	30	0	0
T159	21417	85	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4574	0	0
T70	11570	15	0	0
T71	33765	205	0	0
T116	9861	141	0	0
T119	1941	7	0	0
T120	6481	37	0	0
T121	270748	708	0	0
T156	19847	80	0	0
T157	7481	22	0	0
T158	7362	3	0	0
T159	21417	98	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4390	0	0
T70	11570	89	0	0
T71	33765	197	0	0
T116	9861	104	0	0
T117	3438	12	0	0
T119	1941	7	0	0
T120	6481	38	0	0
T156	19847	31	0	0
T157	7481	6	0	0
T158	7362	18	0	0
T159	21417	63	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4666	0	0
T70	11570	69	0	0
T71	33765	252	0	0
T116	9861	104	0	0
T119	1941	6	0	0
T120	6481	53	0	0
T121	270748	700	0	0
T156	19847	79	0	0
T157	7481	25	0	0
T158	7362	34	0	0
T159	21417	96	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4666	0	0
T70	11570	47	0	0
T71	33765	347	0	0
T116	9861	12	0	0
T117	3438	32	0	0
T119	1941	4	0	0
T120	6481	101	0	0
T156	19847	70	0	0
T157	7481	27	0	0
T158	7362	32	0	0
T159	21417	55	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4454	0	0
T70	11570	91	0	0
T71	33765	312	0	0
T116	9861	85	0	0
T120	6481	34	0	0
T121	270748	671	0	0
T156	19847	60	0	0
T157	7481	8	0	0
T158	7362	24	0	0
T159	21417	27	0	0
T160	11246	79	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4839	0	0
T70	11570	93	0	0
T71	33765	337	0	0
T116	9861	99	0	0
T117	3438	20	0	0
T119	1941	4	0	0
T120	6481	7	0	0
T156	19847	70	0	0
T157	7481	30	0	0
T158	7362	50	0	0
T159	21417	37	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4727	0	0
T70	11570	59	0	0
T71	33765	311	0	0
T116	9861	104	0	0
T117	3438	16	0	0
T119	1941	9	0	0
T120	6481	42	0	0
T156	19847	76	0	0
T157	7481	36	0	0
T158	7362	28	0	0
T159	21417	34	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4385	0	0
T70	11570	92	0	0
T71	33765	363	0	0
T116	9861	42	0	0
T117	3438	20	0	0
T119	1941	6	0	0
T120	6481	57	0	0
T156	19847	71	0	0
T157	7481	20	0	0
T158	7362	6	0	0
T159	21417	63	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4652	0	0
T70	11570	76	0	0
T71	33765	334	0	0
T116	9861	58	0	0
T117	3438	20	0	0
T120	6481	106	0	0
T121	270748	674	0	0
T156	19847	84	0	0
T157	7481	2	0	0
T158	7362	25	0	0
T159	21417	27	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4262	0	0
T70	11570	117	0	0
T71	33765	118	0	0
T116	9861	105	0	0
T117	3438	2	0	0
T119	1941	3	0	0
T120	6481	8	0	0
T156	19847	31	0	0
T157	7481	20	0	0
T158	7362	21	0	0
T159	21417	62	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4743	0	0
T70	11570	79	0	0
T71	33765	224	0	0
T116	9861	4	0	0
T117	3438	18	0	0
T120	6481	99	0	0
T121	270748	656	0	0
T156	19847	66	0	0
T157	7481	2	0	0
T158	7362	7	0	0
T159	21417	70	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4539	0	0
T70	11570	19	0	0
T71	33765	282	0	0
T116	9861	58	0	0
T117	3438	4	0	0
T120	6481	46	0	0
T121	270748	643	0	0
T156	19847	87	0	0
T157	7481	29	0	0
T158	7362	6	0	0
T159	21417	91	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4491	0	0
T70	11570	134	0	0
T71	33765	224	0	0
T116	9861	97	0	0
T117	3438	42	0	0
T120	6481	12	0	0
T121	270748	674	0	0
T156	19847	106	0	0
T157	7481	26	0	0
T158	7362	20	0	0
T159	21417	106	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4568	0	0
T70	11570	42	0	0
T71	33765	272	0	0
T116	9861	77	0	0
T117	3438	7	0	0
T119	1941	5	0	0
T120	6481	65	0	0
T156	19847	118	0	0
T157	7481	24	0	0
T158	7362	12	0	0
T159	21417	86	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4277	0	0
T70	11570	107	0	0
T71	33765	246	0	0
T116	9861	57	0	0
T117	3438	3	0	0
T119	1941	5	0	0
T120	6481	50	0	0
T156	19847	65	0	0
T157	7481	12	0	0
T158	7362	7	0	0
T159	21417	49	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4748	0	0
T70	11570	16	0	0
T71	33765	424	0	0
T116	9861	82	0	0
T120	6481	4	0	0
T121	270748	639	0	0
T156	19847	89	0	0
T157	7481	5	0	0
T158	7362	13	0	0
T159	21417	59	0	0
T160	11246	130	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4508	0	0
T70	11570	62	0	0
T71	33765	128	0	0
T116	9861	50	0	0
T117	3438	29	0	0
T119	1941	2	0	0
T120	6481	9	0	0
T156	19847	51	0	0
T157	7481	20	0	0
T158	7362	32	0	0
T159	21417	50	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4550	0	0
T70	11570	105	0	0
T71	33765	303	0	0
T116	9861	53	0	0
T117	3438	3	0	0
T120	6481	12	0	0
T121	270748	660	0	0
T156	19847	74	0	0
T157	7481	15	0	0
T158	7362	9	0	0
T159	21417	33	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4242	0	0
T70	11570	53	0	0
T71	33765	224	0	0
T116	9861	93	0	0
T117	3438	3	0	0
T119	1941	8	0	0
T120	6481	14	0	0
T156	19847	73	0	0
T157	7481	14	0	0
T158	7362	31	0	0
T159	21417	51	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2391	0	0
T70	11570	20	0	0
T71	33765	52	0	0
T116	9861	5	0	0
T117	3438	7	0	0
T119	1941	6	0	0
T120	6481	7	0	0
T156	19847	119	0	0
T157	7481	16	0	0
T158	7362	21	0	0
T159	21417	28	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2435	0	0
T70	11570	27	0	0
T71	33765	51	0	0
T116	9861	14	0	0
T117	3438	5	0	0
T119	1941	6	0	0
T120	6481	3	0	0
T156	19847	30	0	0
T157	7481	38	0	0
T158	7362	13	0	0
T159	21417	87	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2369	0	0
T70	11570	27	0	0
T71	33765	41	0	0
T116	9861	25	0	0
T117	3438	5	0	0
T120	6481	15	0	0
T121	270748	735	0	0
T156	19847	81	0	0
T157	7481	39	0	0
T158	7362	13	0	0
T159	21417	43	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2196	0	0
T70	11570	27	0	0
T71	33765	53	0	0
T116	9861	24	0	0
T117	3438	3	0	0
T119	1941	1	0	0
T120	6481	20	0	0
T156	19847	41	0	0
T157	7481	21	0	0
T158	7362	5	0	0
T159	21417	14	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2853	0	0
T70	11570	22	0	0
T71	33765	73	0	0
T116	9861	36	0	0
T117	3438	7	0	0
T119	1941	5	0	0
T120	6481	6	0	0
T156	19847	76	0	0
T157	7481	28	0	0
T158	7362	47	0	0
T159	21417	68	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	4598	0	0
T20	4607	24	0	0
T21	414214	0	0	0
T145	0	6	0	0
T161	0	32	0	0
T162	0	42	0	0
T163	0	34	0	0
T164	0	9	0	0
T165	0	14	0	0
T166	0	62	0	0
T167	0	28	0	0
T168	0	19	0	0
T169	123909	0	0	0
T170	344014	0	0	0
T171	101899	0	0	0
T172	554197	0	0	0
T173	424295	0	0	0
T174	11572	0	0	0
T175	71934	0	0	0
T176	11338	0	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2373	0	0
T70	11570	26	0	0
T71	33765	48	0	0
T116	9861	16	0	0
T119	1941	8	0	0
T120	6481	15	0	0
T121	270748	710	0	0
T156	19847	31	0	0
T157	7481	12	0	0
T158	7362	11	0	0
T159	21417	103	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2368	0	0
T70	11570	26	0	0
T71	33765	59	0	0
T116	9861	24	0	0
T117	3438	2	0	0
T119	1941	5	0	0
T120	6481	13	0	0
T156	19847	45	0	0
T157	7481	5	0	0
T158	7362	29	0	0
T159	21417	56	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2067	0	0
T70	11570	24	0	0
T71	33765	37	0	0
T116	9861	15	0	0
T117	3438	1	0	0
T119	1941	6	0	0
T120	6481	7	0	0
T156	19847	45	0	0
T157	7481	5	0	0
T158	7362	8	0	0
T159	21417	90	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2068	0	0
T70	11570	6	0	0
T71	33765	41	0	0
T116	9861	12	0	0
T119	1941	4	0	0
T120	6481	5	0	0
T121	270748	668	0	0
T156	19847	93	0	0
T157	7481	24	0	0
T158	7362	6	0	0
T159	21417	36	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2051	0	0
T70	11570	18	0	0
T71	33765	40	0	0
T116	9861	15	0	0
T119	1941	6	0	0
T120	6481	4	0	0
T121	270748	605	0	0
T156	19847	28	0	0
T157	7481	34	0	0
T158	7362	11	0	0
T159	21417	58	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2175	0	0
T70	11570	17	0	0
T71	33765	36	0	0
T116	9861	12	0	0
T117	3438	5	0	0
T119	1941	2	0	0
T120	6481	17	0	0
T156	19847	80	0	0
T157	7481	10	0	0
T158	7362	32	0	0
T159	21417	61	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2590	0	0
T70	11570	30	0	0
T71	33765	60	0	0
T116	9861	19	0	0
T119	1941	6	0	0
T120	6481	29	0	0
T121	270748	655	0	0
T156	19847	41	0	0
T157	7481	4	0	0
T158	7362	39	0	0
T159	21417	88	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2111	0	0
T70	11570	23	0	0
T71	33765	23	0	0
T116	9861	7	0	0
T117	3438	4	0	0
T119	1941	6	0	0
T120	6481	3	0	0
T156	19847	96	0	0
T157	7481	21	0	0
T158	7362	26	0	0
T159	21417	72	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	3187	0	0
T70	11570	49	0	0
T71	33765	178	0	0
T116	9861	40	0	0
T117	3438	1	0	0
T119	1941	9	0	0
T120	6481	8	0	0
T156	19847	27	0	0
T157	7481	34	0	0
T158	7362	31	0	0
T159	21417	78	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2420	0	0
T70	11570	30	0	0
T71	33765	43	0	0
T116	9861	27	0	0
T117	3438	8	0	0
T119	1941	3	0	0
T120	6481	11	0	0
T156	19847	72	0	0
T157	7481	37	0	0
T158	7362	38	0	0
T159	21417	86	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2108	0	0
T70	11570	15	0	0
T71	33765	62	0	0
T116	9861	18	0	0
T117	3438	1	0	0
T120	6481	9	0	0
T121	270748	696	0	0
T156	19847	68	0	0
T157	7481	23	0	0
T158	7362	22	0	0
T159	21417	49	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2114	0	0
T70	11570	10	0	0
T71	33765	31	0	0
T116	9861	15	0	0
T120	6481	1	0	0
T121	270748	685	0	0
T156	19847	91	0	0
T157	7481	49	0	0
T158	7362	6	0	0
T159	21417	56	0	0
T160	11246	13	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2092	0	0
T70	11570	16	0	0
T71	33765	35	0	0
T116	9861	19	0	0
T117	3438	4	0	0
T119	1941	6	0	0
T120	6481	4	0	0
T156	19847	47	0	0
T157	7481	22	0	0
T158	7362	27	0	0
T159	21417	83	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2150	0	0
T70	11570	21	0	0
T71	33765	38	0	0
T116	9861	13	0	0
T117	3438	5	0	0
T119	1941	3	0	0
T120	6481	6	0	0
T156	19847	64	0	0
T157	7481	11	0	0
T158	7362	57	0	0
T159	21417	73	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2120	0	0
T70	11570	9	0	0
T71	33765	25	0	0
T116	9861	21	0	0
T119	1941	5	0	0
T120	6481	7	0	0
T121	270748	689	0	0
T156	19847	74	0	0
T157	7481	12	0	0
T158	7362	28	0	0
T159	21417	77	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458380983	2119	0	0
T70	11570	7	0	0
T71	33765	45	0	0
T116	9861	13	0	0
T119	1941	1	0	0
T120	6481	12	0	0
T121	270748	699	0	0
T156	19847	103	0	0
T157	7481	7	0	0
T158	7362	34	0	0
T159	21417	40	0	0