Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3838489	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4574533

1

T1

1630

T2

3176

T3

903

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4645169	1			T1	1430		T2	4529		T3	37
values[0x0]	1882784	1			T1	469		T2	446		T3	453
values[0x1]	1885069	1			T1	443		T2	470		T3	432

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2727338	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5685684

1

T1

1764

T2

3633

T3

906

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32916	1			T2	24		T3	12		T7	3
valid_sources[0x01]	29411	1			T2	27		T4	20		T7	424
valid_sources[0x02]	30567	1			T2	15		T3	5		T7	176
valid_sources[0x03]	29993	1			T2	17		T6	1		T7	58
valid_sources[0x04]	29547	1			T2	22		T3	6		T4	7
valid_sources[0x05]	32488	1			T2	12		T3	3		T8	448
valid_sources[0x06]	29625	1			T2	32		T3	6		T4	5
valid_sources[0x07]	32555	1			T2	11		T3	3		T7	22
valid_sources[0x08]	32495	1			T2	19		T7	558		T8	477
valid_sources[0x09]	32725	1			T2	23		T5	40		T7	114
valid_sources[0x0a]	33370	1			T2	34		T3	11		T5	91
valid_sources[0x0b]	35763	1			T2	14		T3	5		T7	414
valid_sources[0x0c]	33085	1			T2	15		T3	2		T7	21
valid_sources[0x0d]	32925	1			T2	27		T3	3		T5	1013
valid_sources[0x0e]	31735	1			T2	33		T3	2		T7	23
valid_sources[0x0f]	32104	1			T2	14		T3	7		T6	2
valid_sources[0x10]	33551	1			T2	13		T3	3		T5	4
valid_sources[0x11]	35733	1			T2	13		T3	8		T7	3
valid_sources[0x12]	30065	1			T2	19		T5	9		T7	23
valid_sources[0x13]	30201	1			T2	10		T7	5		T8	401
valid_sources[0x14]	34241	1			T2	21		T7	71		T8	420
valid_sources[0x15]	31280	1			T2	9		T3	2		T5	78
valid_sources[0x16]	32215	1			T2	31		T3	11		T7	152
valid_sources[0x17]	35753	1			T2	21		T3	8		T7	49
valid_sources[0x18]	32060	1			T2	22		T5	153		T7	40
valid_sources[0x19]	32981	1			T2	49		T3	3		T7	71
valid_sources[0x1a]	35703	1			T2	21		T3	2		T5	9
valid_sources[0x1b]	33269	1			T2	31		T3	1		T5	1
valid_sources[0x1c]	31879	1			T2	23		T5	418		T7	211
valid_sources[0x1d]	33322	1			T2	19		T7	32		T8	407
valid_sources[0x1e]	32198	1			T2	16		T5	1		T7	86
valid_sources[0x1f]	31116	1			T2	32		T3	4		T7	2
valid_sources[0x20]	31223	1			T2	24		T3	4		T7	1
valid_sources[0x21]	32931	1			T2	29		T3	1		T5	4
valid_sources[0x22]	32250	1			T2	36		T7	67		T8	503
valid_sources[0x23]	33112	1			T2	34		T3	14		T7	102
valid_sources[0x24]	33788	1			T2	21		T5	480		T7	92
valid_sources[0x25]	38509	1			T2	16		T3	12		T7	56
valid_sources[0x26]	31667	1			T2	34		T3	6		T7	69
valid_sources[0x27]	29874	1			T2	16		T3	16		T4	17
valid_sources[0x28]	30995	1			T2	25		T3	1		T5	23
valid_sources[0x29]	29712	1			T2	32		T3	1		T4	37
valid_sources[0x2a]	37461	1			T2	21		T3	14		T4	15
valid_sources[0x2b]	31741	1			T2	37		T3	15		T5	60
valid_sources[0x2c]	32141	1			T2	7		T3	1		T7	2
valid_sources[0x2d]	31793	1			T2	17		T5	1		T7	42
valid_sources[0x2e]	30934	1			T2	23		T3	6		T5	1
valid_sources[0x2f]	30806	1			T2	33		T3	12		T7	5
valid_sources[0x30]	33655	1			T2	27		T3	3		T5	2
valid_sources[0x31]	32465	1			T2	16		T5	2		T7	66
valid_sources[0x32]	31674	1			T2	6		T3	5		T7	21
valid_sources[0x33]	36294	1			T2	8		T4	2		T7	54
valid_sources[0x34]	31875	1			T2	19		T7	141		T8	445
valid_sources[0x35]	29161	1			T2	16		T7	20		T8	434
valid_sources[0x36]	38239	1			T2	17		T3	3		T5	7
valid_sources[0x37]	34831	1			T2	25		T3	3		T7	1
valid_sources[0x38]	32007	1			T2	18		T3	4		T7	11
valid_sources[0x39]	35430	1			T2	13		T3	2		T6	3
valid_sources[0x3a]	31538	1			T2	15		T3	1		T7	743
valid_sources[0x3b]	31794	1			T2	20		T7	34		T8	381
valid_sources[0x3c]	30720	1			T2	11		T5	1		T7	473
valid_sources[0x3d]	31078	1			T2	18		T3	2		T7	28
valid_sources[0x3e]	33171	1			T2	41		T3	7		T4	10
valid_sources[0x3f]	30556	1			T2	14		T3	5		T7	3
valid_sources[0x40]	29511	1			T2	11		T3	17		T6	1
valid_sources[0x41]	29027	1			T2	22		T7	46		T8	457
valid_sources[0x42]	31168	1			T2	15		T3	1		T7	55
valid_sources[0x43]	32416	1			T2	16		T3	3		T7	193
valid_sources[0x44]	41021	1			T2	17		T3	6		T7	43
valid_sources[0x45]	36477	1			T2	10		T3	1		T4	5
valid_sources[0x46]	29520	1			T2	23		T3	1		T5	91
valid_sources[0x47]	30353	1			T2	13		T5	1		T7	48
valid_sources[0x48]	31097	1			T2	40		T7	4		T8	434
valid_sources[0x49]	31837	1			T2	12		T3	3		T7	13
valid_sources[0x4a]	31474	1			T2	29		T3	4		T5	106
valid_sources[0x4b]	31820	1			T2	19		T4	2		T7	138
valid_sources[0x4c]	30175	1			T2	20		T3	1		T4	3
valid_sources[0x4d]	29725	1			T2	41		T3	7		T7	74
valid_sources[0x4e]	34312	1			T2	21		T3	2		T4	19
valid_sources[0x4f]	31794	1			T1	909		T2	12		T7	5
valid_sources[0x50]	33044	1			T2	20		T3	2		T7	139
valid_sources[0x51]	35451	1			T2	19		T3	3		T7	2
valid_sources[0x52]	36476	1			T2	24		T3	3		T7	7
valid_sources[0x53]	32817	1			T2	20		T3	22		T7	62
valid_sources[0x54]	65885	1			T2	17		T3	8		T7	110
valid_sources[0x55]	32885	1			T2	25		T3	2		T5	1
valid_sources[0x56]	29828	1			T2	16		T5	80		T7	134
valid_sources[0x57]	34746	1			T2	26		T3	2		T4	24
valid_sources[0x58]	44614	1			T2	24		T3	2		T4	1
valid_sources[0x59]	33028	1			T2	17		T3	2		T5	109
valid_sources[0x5a]	36198	1			T2	31		T5	128		T7	139
valid_sources[0x5b]	35081	1			T2	16		T3	5		T6	1
valid_sources[0x5c]	32380	1			T2	28		T3	4		T7	139
valid_sources[0x5d]	37969	1			T2	22		T7	1		T8	464
valid_sources[0x5e]	31392	1			T2	12		T3	1		T7	283
valid_sources[0x5f]	31263	1			T2	15		T3	7		T5	453
valid_sources[0x60]	36069	1			T2	20		T5	1		T7	182
valid_sources[0x61]	31519	1			T2	14		T3	1		T5	6
valid_sources[0x62]	33651	1			T2	18		T3	1		T7	17
valid_sources[0x63]	29536	1			T2	21		T3	3		T7	326
valid_sources[0x64]	33589	1			T2	6		T7	11		T8	514
valid_sources[0x65]	29624	1			T2	33		T3	4		T7	34
valid_sources[0x66]	32717	1			T2	27		T5	4		T7	112
valid_sources[0x67]	32160	1			T2	4		T3	4		T7	153
valid_sources[0x68]	30986	1			T2	18		T3	7		T8	456
valid_sources[0x69]	32120	1			T2	18		T3	8		T7	279
valid_sources[0x6a]	30681	1			T2	16		T7	1		T8	421
valid_sources[0x6b]	31496	1			T2	20		T3	9		T7	4
valid_sources[0x6c]	32720	1			T2	13		T3	3		T7	15
valid_sources[0x6d]	33090	1			T2	19		T3	8		T4	15
valid_sources[0x6e]	33944	1			T2	20		T3	2		T5	1
valid_sources[0x6f]	32548	1			T2	10		T3	2		T7	61
valid_sources[0x70]	30609	1			T2	21		T5	3		T7	233
valid_sources[0x71]	32169	1			T2	30		T3	10		T7	42
valid_sources[0x72]	31837	1			T2	18		T3	1		T7	164
valid_sources[0x73]	30331	1			T2	30		T5	1		T7	8
valid_sources[0x74]	28574	1			T2	20		T3	7		T5	4
valid_sources[0x75]	34975	1			T2	26		T3	11		T7	15
valid_sources[0x76]	39885	1			T2	27		T3	17		T7	10
valid_sources[0x77]	30928	1			T2	21		T3	2		T7	13
valid_sources[0x78]	30052	1			T2	19		T3	9		T7	50
valid_sources[0x79]	30773	1			T2	18		T7	68		T8	332
valid_sources[0x7a]	32657	1			T2	12		T3	3		T5	2
valid_sources[0x7b]	32217	1			T2	35		T3	4		T7	128
valid_sources[0x7c]	32964	1			T2	40		T3	3		T7	2
valid_sources[0x7d]	32551	1			T2	13		T3	4		T7	7
valid_sources[0x7e]	32048	1			T2	32		T4	1		T7	3
valid_sources[0x7f]	29867	1			T2	14		T3	2		T6	1
valid_sources[0x80]	30699	1			T2	23		T3	3		T6	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1151220

1

T1

722

T2

2268

T3

20

values[0x0]

all_enables

biggest_size

1722934

1

T1

468

T2

444

T3

453

values[0x1]

all_enables

biggest_size

1700379

1

T1

440

T2

464

T3

430