Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3857322

1

T1

712

T2

2269

T3

19

full_word

4575723

1

T1

1630

T2

3176

T3

903

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8432635	1			T1	2342		T2	5445		T3	922
auto[TlIntgErrCmd]	130	1			T80	3		T81	4		T83	6
auto[TlIntgErrData]	155	1			T80	13		T81	2		T83	9
auto[TlIntgErrBoth]	125	1			T80	4		T81	4		T83	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4648696

1

T1

1430

T2

4529

T3

37

auto[1]

3784349

1

T1

912

T2

916

T3

885

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3497032	1			T1	708		T2	2261		T3	17
auto[TlIntgErrNone]	partial	auto[1]	359907	1			T1	4		T2	8		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	1151483	1			T1	722		T2	2268		T3	20
auto[TlIntgErrNone]	full_word	auto[1]	3424213	1			T1	908		T2	908		T3	883
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T80	2		T81	3		T83	3
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T80	1		T83	3		T149	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T152	2		T151	1		T153	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T81	1		T154	1		T155	1
auto[TlIntgErrData]	partial	auto[0]	72	1			T80	4		T81	2		T83	4
auto[TlIntgErrData]	partial	auto[1]	72	1			T80	7		T83	5		T149	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T156	1		T157	3		T153	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T80	2		T156	1		T158	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T81	1		T83	3		T149	1
auto[TlIntgErrBoth]	partial	auto[1]	74	1			T80	4		T81	3		T149	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T149	2		T134	1		T151	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T83	2		T154	1		-	-