Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	665147830	3508914	0	0
gen_wmask[1].MaskCheckPortA_A	665147830	3508914	0	0
gen_wmask[2].MaskCheckPortA_A	665147830	3508914	0	0
gen_wmask[3].MaskCheckPortA_A	665147830	3508914	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665147830	3508914	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	8994	268	0	0
T5	368886	3826	0	0
T6	3568	0	0	0
T7	1266799	19627	0	0
T8	1334214	14939	0	0
T9	50545	832	0	0
T10	32630	1344	0	0
T12	37907	0	0	0
T13	477045	1038	0	0
T14	0	13450	0	0
T22	1288	46	0	0
T26	0	4961	0	0
T30	0	2773	0	0
T35	0	4120	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665147830	3508914	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	8994	268	0	0
T5	368886	3826	0	0
T6	3568	0	0	0
T7	1266799	19627	0	0
T8	1334214	14939	0	0
T9	50545	832	0	0
T10	32630	1344	0	0
T12	37907	0	0	0
T13	477045	1038	0	0
T14	0	13450	0	0
T22	1288	46	0	0
T26	0	4961	0	0
T30	0	2773	0	0
T35	0	4120	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665147830	3508914	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	8994	268	0	0
T5	368886	3826	0	0
T6	3568	0	0	0
T7	1266799	19627	0	0
T8	1334214	14939	0	0
T9	50545	832	0	0
T10	32630	1344	0	0
T12	37907	0	0	0
T13	477045	1038	0	0
T14	0	13450	0	0
T22	1288	46	0	0
T26	0	4961	0	0
T30	0	2773	0	0
T35	0	4120	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665147830	3508914	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	8994	268	0	0
T5	368886	3826	0	0
T6	3568	0	0	0
T7	1266799	19627	0	0
T8	1334214	14939	0	0
T9	50545	832	0	0
T10	32630	1344	0	0
T12	37907	0	0	0
T13	477045	1038	0	0
T14	0	13450	0	0
T22	1288	46	0	0
T26	0	4961	0	0
T30	0	2773	0	0
T35	0	4120	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	505598728	2233877	0	0
gen_wmask[1].MaskCheckPortA_A	505598728	2233877	0	0
gen_wmask[2].MaskCheckPortA_A	505598728	2233877	0	0
gen_wmask[3].MaskCheckPortA_A	505598728	2233877	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505598728	2233877	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	3338	43	0	0
T5	130306	3624	0	0
T6	2718	0	0	0
T7	677443	9470	0	0
T8	550770	9704	0	0
T9	27079	832	0	0
T10	15466	1344	0	0
T22	0	28	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505598728	2233877	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	3338	43	0	0
T5	130306	3624	0	0
T6	2718	0	0	0
T7	677443	9470	0	0
T8	550770	9704	0	0
T9	27079	832	0	0
T10	15466	1344	0	0
T22	0	28	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505598728	2233877	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	3338	43	0	0
T5	130306	3624	0	0
T6	2718	0	0	0
T7	677443	9470	0	0
T8	550770	9704	0	0
T9	27079	832	0	0
T10	15466	1344	0	0
T22	0	28	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505598728	2233877	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	3338	43	0	0
T5	130306	3624	0	0
T6	2718	0	0	0
T7	677443	9470	0	0
T8	550770	9704	0	0
T9	27079	832	0	0
T10	15466	1344	0	0
T22	0	28	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	159549102	1275037	0	0
gen_wmask[1].MaskCheckPortA_A	159549102	1275037	0	0
gen_wmask[2].MaskCheckPortA_A	159549102	1275037	0	0
gen_wmask[3].MaskCheckPortA_A	159549102	1275037	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	1275037	0	0
T4	5656	225	0	0
T5	238580	202	0	0
T6	850	0	0	0
T7	589356	10157	0	0
T8	783444	5235	0	0
T9	23466	0	0	0
T10	17164	0	0	0
T12	37907	0	0	0
T13	477045	1038	0	0
T14	0	13450	0	0
T22	1288	18	0	0
T26	0	4961	0	0
T30	0	2773	0	0
T35	0	4120	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	1275037	0	0
T4	5656	225	0	0
T5	238580	202	0	0
T6	850	0	0	0
T7	589356	10157	0	0
T8	783444	5235	0	0
T9	23466	0	0	0
T10	17164	0	0	0
T12	37907	0	0	0
T13	477045	1038	0	0
T14	0	13450	0	0
T22	1288	18	0	0
T26	0	4961	0	0
T30	0	2773	0	0
T35	0	4120	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	1275037	0	0
T4	5656	225	0	0
T5	238580	202	0	0
T6	850	0	0	0
T7	589356	10157	0	0
T8	783444	5235	0	0
T9	23466	0	0	0
T10	17164	0	0	0
T12	37907	0	0	0
T13	477045	1038	0	0
T14	0	13450	0	0
T22	1288	18	0	0
T26	0	4961	0	0
T30	0	2773	0	0
T35	0	4120	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	1275037	0	0
T4	5656	225	0	0
T5	238580	202	0	0
T6	850	0	0	0
T7	589356	10157	0	0
T8	783444	5235	0	0
T9	23466	0	0	0
T10	17164	0	0	0
T12	37907	0	0	0
T13	477045	1038	0	0
T14	0	13450	0	0
T22	1288	18	0	0
T26	0	4961	0	0
T30	0	2773	0	0
T35	0	4120	0	0