Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	507900933	3111239	0	0
DepthKnown_A	507900933	507768984	0	0
RvalidKnown_A	507900933	507768984	0	0
WreadyKnown_A	507900933	507768984	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	3111239	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	3338	0	0	0
T5	130306	4990	0	0
T6	2718	0	0	0
T7	677443	13314	0	0
T8	550770	10820	0	0
T9	27079	1663	0	0
T10	15466	1854	0	0
T12	0	832	0	0
T13	0	7484	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	507768984	0	0
T1	41405	41354	0	0
T2	95610	95559	0	0
T3	28002	27945	0	0
T4	3338	3254	0	0
T5	130306	130215	0	0
T6	2718	2649	0	0
T7	677443	677389	0	0
T8	550770	550763	0	0
T9	27079	27014	0	0
T10	15466	15400	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	507768984	0	0
T1	41405	41354	0	0
T2	95610	95559	0	0
T3	28002	27945	0	0
T4	3338	3254	0	0
T5	130306	130215	0	0
T6	2718	2649	0	0
T7	677443	677389	0	0
T8	550770	550763	0	0
T9	27079	27014	0	0
T10	15466	15400	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	507768984	0	0
T1	41405	41354	0	0
T2	95610	95559	0	0
T3	28002	27945	0	0
T4	3338	3254	0	0
T5	130306	130215	0	0
T6	2718	2649	0	0
T7	677443	677389	0	0
T8	550770	550763	0	0
T9	27079	27014	0	0
T10	15466	15400	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	507900933	3597305	0	0
DepthKnown_A	507900933	507768984	0	0
RvalidKnown_A	507900933	507768984	0	0
WreadyKnown_A	507900933	507768984	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	3597305	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	3338	0	0	0
T5	130306	3328	0	0
T6	2718	0	0	0
T7	677443	20392	0	0
T8	550770	23032	0	0
T9	27079	832	0	0
T10	15466	1344	0	0
T12	0	2628	0	0
T13	0	4160	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	507768984	0	0
T1	41405	41354	0	0
T2	95610	95559	0	0
T3	28002	27945	0	0
T4	3338	3254	0	0
T5	130306	130215	0	0
T6	2718	2649	0	0
T7	677443	677389	0	0
T8	550770	550763	0	0
T9	27079	27014	0	0
T10	15466	15400	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	507768984	0	0
T1	41405	41354	0	0
T2	95610	95559	0	0
T3	28002	27945	0	0
T4	3338	3254	0	0
T5	130306	130215	0	0
T6	2718	2649	0	0
T7	677443	677389	0	0
T8	550770	550763	0	0
T9	27079	27014	0	0
T10	15466	15400	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	507768984	0	0
T1	41405	41354	0	0
T2	95610	95559	0	0
T3	28002	27945	0	0
T4	3338	3254	0	0
T5	130306	130215	0	0
T6	2718	2649	0	0
T7	677443	677389	0	0
T8	550770	550763	0	0
T9	27079	27014	0	0
T10	15466	15400	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	507900933	188561	0	0
DepthKnown_A	507900933	507768984	0	0
RvalidKnown_A	507900933	507768984	0	0
WreadyKnown_A	507900933	507768984	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	188561	0	0
T4	3338	59	0	0
T5	130306	52	0	0
T6	2718	0	0	0
T7	677443	1349	0	0
T8	550770	743	0	0
T9	27079	0	0	0
T10	15466	0	0	0
T11	7743	0	0	0
T12	49083	0	0	0
T13	0	193	0	0
T14	0	1234	0	0
T22	6187	5	0	0
T26	0	698	0	0
T30	0	184	0	0
T35	0	405	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	507768984	0	0
T1	41405	41354	0	0
T2	95610	95559	0	0
T3	28002	27945	0	0
T4	3338	3254	0	0
T5	130306	130215	0	0
T6	2718	2649	0	0
T7	677443	677389	0	0
T8	550770	550763	0	0
T9	27079	27014	0	0
T10	15466	15400	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	507768984	0	0
T1	41405	41354	0	0
T2	95610	95559	0	0
T3	28002	27945	0	0
T4	3338	3254	0	0
T5	130306	130215	0	0
T6	2718	2649	0	0
T7	677443	677389	0	0
T8	550770	550763	0	0
T9	27079	27014	0	0
T10	15466	15400	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	507768984	0	0
T1	41405	41354	0	0
T2	95610	95559	0	0
T3	28002	27945	0	0
T4	3338	3254	0	0
T5	130306	130215	0	0
T6	2718	2649	0	0
T7	677443	677389	0	0
T8	550770	550763	0	0
T9	27079	27014	0	0
T10	15466	15400	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	507900933	461645	0	0
DepthKnown_A	507900933	507768984	0	0
RvalidKnown_A	507900933	507768984	0	0
WreadyKnown_A	507900933	507768984	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	461645	0	0
T4	3338	59	0	0
T5	130306	52	0	0
T6	2718	0	0	0
T7	677443	6033	0	0
T8	550770	2804	0	0
T9	27079	0	0	0
T10	15466	0	0	0
T11	7743	0	0	0
T12	49083	0	0	0
T13	0	193	0	0
T14	0	1234	0	0
T22	6187	5	0	0
T26	0	698	0	0
T30	0	333	0	0
T35	0	405	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	507768984	0	0
T1	41405	41354	0	0
T2	95610	95559	0	0
T3	28002	27945	0	0
T4	3338	3254	0	0
T5	130306	130215	0	0
T6	2718	2649	0	0
T7	677443	677389	0	0
T8	550770	550763	0	0
T9	27079	27014	0	0
T10	15466	15400	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	507768984	0	0
T1	41405	41354	0	0
T2	95610	95559	0	0
T3	28002	27945	0	0
T4	3338	3254	0	0
T5	130306	130215	0	0
T6	2718	2649	0	0
T7	677443	677389	0	0
T8	550770	550763	0	0
T9	27079	27014	0	0
T10	15466	15400	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	507768984	0	0
T1	41405	41354	0	0
T2	95610	95559	0	0
T3	28002	27945	0	0
T4	3338	3254	0	0
T5	130306	130215	0	0
T6	2718	2649	0	0
T7	677443	677389	0	0
T8	550770	550763	0	0
T9	27079	27014	0	0
T10	15466	15400	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	507900933	6647395	0	0
DepthKnown_A	507900933	507768984	0	0
RvalidKnown_A	507900933	507768984	0	0
WreadyKnown_A	507900933	507768984	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	6647395	0	0
T1	41405	1511	0	0
T2	95610	4613	0	0
T3	28002	92	0	0
T4	3338	230	0	0
T5	130306	1907	0	0
T6	2718	26	0	0
T7	677443	16733	0	0
T8	550770	110039	0	0
T9	27079	693	0	0
T10	15466	619	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	507768984	0	0
T1	41405	41354	0	0
T2	95610	95559	0	0
T3	28002	27945	0	0
T4	3338	3254	0	0
T5	130306	130215	0	0
T6	2718	2649	0	0
T7	677443	677389	0	0
T8	550770	550763	0	0
T9	27079	27014	0	0
T10	15466	15400	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	507768984	0	0
T1	41405	41354	0	0
T2	95610	95559	0	0
T3	28002	27945	0	0
T4	3338	3254	0	0
T5	130306	130215	0	0
T6	2718	2649	0	0
T7	677443	677389	0	0
T8	550770	550763	0	0
T9	27079	27014	0	0
T10	15466	15400	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	507768984	0	0
T1	41405	41354	0	0
T2	95610	95559	0	0
T3	28002	27945	0	0
T4	3338	3254	0	0
T5	130306	130215	0	0
T6	2718	2649	0	0
T7	677443	677389	0	0
T8	550770	550763	0	0
T9	27079	27014	0	0
T10	15466	15400	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	507900933	15671082	0	0
DepthKnown_A	507900933	507768984	0	0
RvalidKnown_A	507900933	507768984	0	0
WreadyKnown_A	507900933	507768984	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	15671082	0	0
T1	41405	1510	0	0
T2	95610	4613	0	0
T3	28002	90	0	0
T4	3338	230	0	0
T5	130306	1881	0	0
T6	2718	26	0	0
T7	677443	64840	0	0
T8	550770	393986	0	0
T9	27079	693	0	0
T10	15466	1860	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	507768984	0	0
T1	41405	41354	0	0
T2	95610	95559	0	0
T3	28002	27945	0	0
T4	3338	3254	0	0
T5	130306	130215	0	0
T6	2718	2649	0	0
T7	677443	677389	0	0
T8	550770	550763	0	0
T9	27079	27014	0	0
T10	15466	15400	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	507768984	0	0
T1	41405	41354	0	0
T2	95610	95559	0	0
T3	28002	27945	0	0
T4	3338	3254	0	0
T5	130306	130215	0	0
T6	2718	2649	0	0
T7	677443	677389	0	0
T8	550770	550763	0	0
T9	27079	27014	0	0
T10	15466	15400	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	507768984	0	0
T1	41405	41354	0	0
T2	95610	95559	0	0
T3	28002	27945	0	0
T4	3338	3254	0	0
T5	130306	130215	0	0
T6	2718	2649	0	0
T7	677443	677389	0	0
T8	550770	550763	0	0
T9	27079	27014	0	0
T10	15466	15400	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0