Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T4,T5,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T13
1	0	Covered	T5,T7,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T5,T7,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	824696932	663750455	0	0
CheckNGreaterZero_A	2862	2862	0	0
GntImpliesReady_A	824696932	3900378	0	0
GntImpliesValid_A	824696932	3900378	0	0
GrantKnown_A	824696932	663750455	0	0
IdxKnown_A	824696932	663750455	0	0
IndexIsCorrect_A	824696932	3900378	0	0
LockArbDecision_A	824696932	0	0	0
NoReadyValidNoGrant_A	824696932	0	0	0
ReadyAndValidImplyGrant_A	824696932	3900378	0	0
ReqAndReadyImplyGrant_A	824696932	3900378	0	0
ReqImpliesValid_A	824696932	3900378	0	0
ReqStaysHighUntilGranted0_M	824696932	0	0	0
RoundRobin_A	824696932	4	0	954
ValidKnown_A	824696932	663750455	0	0
gen_data_port_assertion.DataFlow_A	824696932	3900378	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824696932	663750455	0	0
T1	58065	57978	0	0
T2	124822	124263	0	0
T3	110511	109545	0	0
T4	14650	8910	0	0
T5	607466	366528	0	0
T6	4418	3225	0	0
T7	1856155	1257720	0	0
T8	2117658	1328353	0	0
T9	74011	50464	0	0
T10	49794	32169	0	0
T12	37907	37472	0	0
T13	477045	476695	0	0
T14	0	160808	0	0
T22	1288	1288	0	0
T23	0	48072	0	0
T26	0	89816	0	0
T30	0	18192	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2862	2862	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824696932	3900378	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	8994	373	0	0
T5	607466	4198	0	0
T6	4418	0	0	0
T7	1856155	22214	0	0
T8	2117658	17207	0	0
T9	74011	832	0	0
T10	49794	1344	0	0
T12	75814	0	0	0
T13	954090	1038	0	0
T14	0	15147	0	0
T15	0	12558	0	0
T22	2576	81	0	0
T23	52026	0	0	0
T26	0	5758	0	0
T30	0	2907	0	0
T35	0	4120	0	0
T42	0	64	0	0
T43	0	571	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824696932	3900378	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	8994	373	0	0
T5	607466	4198	0	0
T6	4418	0	0	0
T7	1856155	22214	0	0
T8	2117658	17207	0	0
T9	74011	832	0	0
T10	49794	1344	0	0
T12	75814	0	0	0
T13	954090	1038	0	0
T14	0	15147	0	0
T15	0	12558	0	0
T22	2576	81	0	0
T23	52026	0	0	0
T26	0	5758	0	0
T30	0	2907	0	0
T35	0	4120	0	0
T42	0	64	0	0
T43	0	571	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824696932	663750455	0	0
T1	58065	57978	0	0
T2	124822	124263	0	0
T3	110511	109545	0	0
T4	14650	8910	0	0
T5	607466	366528	0	0
T6	4418	3225	0	0
T7	1856155	1257720	0	0
T8	2117658	1328353	0	0
T9	74011	50464	0	0
T10	49794	32169	0	0
T12	37907	37472	0	0
T13	477045	476695	0	0
T14	0	160808	0	0
T22	1288	1288	0	0
T23	0	48072	0	0
T26	0	89816	0	0
T30	0	18192	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824696932	663750455	0	0
T1	58065	57978	0	0
T2	124822	124263	0	0
T3	110511	109545	0	0
T4	14650	8910	0	0
T5	607466	366528	0	0
T6	4418	3225	0	0
T7	1856155	1257720	0	0
T8	2117658	1328353	0	0
T9	74011	50464	0	0
T10	49794	32169	0	0
T12	37907	37472	0	0
T13	477045	476695	0	0
T14	0	160808	0	0
T22	1288	1288	0	0
T23	0	48072	0	0
T26	0	89816	0	0
T30	0	18192	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824696932	3900378	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	8994	373	0	0
T5	607466	4198	0	0
T6	4418	0	0	0
T7	1856155	22214	0	0
T8	2117658	17207	0	0
T9	74011	832	0	0
T10	49794	1344	0	0
T12	75814	0	0	0
T13	954090	1038	0	0
T14	0	15147	0	0
T15	0	12558	0	0
T22	2576	81	0	0
T23	52026	0	0	0
T26	0	5758	0	0
T30	0	2907	0	0
T35	0	4120	0	0
T42	0	64	0	0
T43	0	571	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824696932	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824696932	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824696932	3900378	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	8994	373	0	0
T5	607466	4198	0	0
T6	4418	0	0	0
T7	1856155	22214	0	0
T8	2117658	17207	0	0
T9	74011	832	0	0
T10	49794	1344	0	0
T12	75814	0	0	0
T13	954090	1038	0	0
T14	0	15147	0	0
T15	0	12558	0	0
T22	2576	81	0	0
T23	52026	0	0	0
T26	0	5758	0	0
T30	0	2907	0	0
T35	0	4120	0	0
T42	0	64	0	0
T43	0	571	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824696932	3900378	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	8994	373	0	0
T5	607466	4198	0	0
T6	4418	0	0	0
T7	1856155	22214	0	0
T8	2117658	17207	0	0
T9	74011	832	0	0
T10	49794	1344	0	0
T12	75814	0	0	0
T13	954090	1038	0	0
T14	0	15147	0	0
T15	0	12558	0	0
T22	2576	81	0	0
T23	52026	0	0	0
T26	0	5758	0	0
T30	0	2907	0	0
T35	0	4120	0	0
T42	0	64	0	0
T43	0	571	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824696932	3900378	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	8994	373	0	0
T5	607466	4198	0	0
T6	4418	0	0	0
T7	1856155	22214	0	0
T8	2117658	17207	0	0
T9	74011	832	0	0
T10	49794	1344	0	0
T12	75814	0	0	0
T13	954090	1038	0	0
T14	0	15147	0	0
T15	0	12558	0	0
T22	2576	81	0	0
T23	52026	0	0	0
T26	0	5758	0	0
T30	0	2907	0	0
T35	0	4120	0	0
T42	0	64	0	0
T43	0	571	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	824696932	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824696932	4	0	954
T17	297518	1	0	1
T18	502646	0	0	1
T19	516254	0	0	1
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	7988	0	0	1
T48	28131	0	0	1
T49	277131	0	0	1
T50	25978	0	0	1
T51	15851	0	0	1
T52	118396	0	0	1
T53	747016	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824696932	663750455	0	0
T1	58065	57978	0	0
T2	124822	124263	0	0
T3	110511	109545	0	0
T4	14650	8910	0	0
T5	607466	366528	0	0
T6	4418	3225	0	0
T7	1856155	1257720	0	0
T8	2117658	1328353	0	0
T9	74011	50464	0	0
T10	49794	32169	0	0
T12	37907	37472	0	0
T13	477045	476695	0	0
T14	0	160808	0	0
T22	1288	1288	0	0
T23	0	48072	0	0
T26	0	89816	0	0
T30	0	18192	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824696932	3900378	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	8994	373	0	0
T5	607466	4198	0	0
T6	4418	0	0	0
T7	1856155	22214	0	0
T8	2117658	17207	0	0
T9	74011	832	0	0
T10	49794	1344	0	0
T12	75814	0	0	0
T13	954090	1038	0	0
T14	0	15147	0	0
T15	0	12558	0	0
T22	2576	81	0	0
T23	52026	0	0	0
T26	0	5758	0	0
T30	0	2907	0	0
T35	0	4120	0	0
T42	0	64	0	0
T43	0	571	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T4,T5,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T7
0	0	1	Unreachable
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	159549102	28293869	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	159549102	625911	0	0
GntImpliesValid_A	159549102	625911	0	0
GrantKnown_A	159549102	28293869	0	0
IdxKnown_A	159549102	28293869	0	0
IndexIsCorrect_A	159549102	625911	0	0
LockArbDecision_A	159549102	0	0	0
NoReadyValidNoGrant_A	159549102	0	0	0
ReadyAndValidImplyGrant_A	159549102	625911	0	0
ReqAndReadyImplyGrant_A	159549102	625911	0	0
ReqImpliesValid_A	159549102	625911	0	0
ReqStaysHighUntilGranted0_M	159549102	0	0	0
RoundRobin_A	159549102	0	0	0
ValidKnown_A	159549102	28293869	0	0
gen_data_port_assertion.DataFlow_A	159549102	625911	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	28293869	0	0
T4	5656	5656	0	0
T5	238580	58600	0	0
T6	850	576	0	0
T7	589356	184024	0	0
T8	783444	84656	0	0
T9	23466	0	0	0
T10	17164	0	0	0
T12	37907	0	0	0
T13	477045	0	0	0
T14	0	160808	0	0
T22	1288	1288	0	0
T23	0	48072	0	0
T26	0	89816	0	0
T30	0	18192	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	625911	0	0
T4	5656	271	0	0
T5	238580	520	0	0
T6	850	0	0	0
T7	589356	4654	0	0
T8	783444	3614	0	0
T9	23466	0	0	0
T10	17164	0	0	0
T12	37907	0	0	0
T13	477045	0	0	0
T14	0	4858	0	0
T15	0	5775	0	0
T22	1288	48	0	0
T26	0	2505	0	0
T30	0	352	0	0
T42	0	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	625911	0	0
T4	5656	271	0	0
T5	238580	520	0	0
T6	850	0	0	0
T7	589356	4654	0	0
T8	783444	3614	0	0
T9	23466	0	0	0
T10	17164	0	0	0
T12	37907	0	0	0
T13	477045	0	0	0
T14	0	4858	0	0
T15	0	5775	0	0
T22	1288	48	0	0
T26	0	2505	0	0
T30	0	352	0	0
T42	0	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	28293869	0	0
T4	5656	5656	0	0
T5	238580	58600	0	0
T6	850	576	0	0
T7	589356	184024	0	0
T8	783444	84656	0	0
T9	23466	0	0	0
T10	17164	0	0	0
T12	37907	0	0	0
T13	477045	0	0	0
T14	0	160808	0	0
T22	1288	1288	0	0
T23	0	48072	0	0
T26	0	89816	0	0
T30	0	18192	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	28293869	0	0
T4	5656	5656	0	0
T5	238580	58600	0	0
T6	850	576	0	0
T7	589356	184024	0	0
T8	783444	84656	0	0
T9	23466	0	0	0
T10	17164	0	0	0
T12	37907	0	0	0
T13	477045	0	0	0
T14	0	160808	0	0
T22	1288	1288	0	0
T23	0	48072	0	0
T26	0	89816	0	0
T30	0	18192	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	625911	0	0
T4	5656	271	0	0
T5	238580	520	0	0
T6	850	0	0	0
T7	589356	4654	0	0
T8	783444	3614	0	0
T9	23466	0	0	0
T10	17164	0	0	0
T12	37907	0	0	0
T13	477045	0	0	0
T14	0	4858	0	0
T15	0	5775	0	0
T22	1288	48	0	0
T26	0	2505	0	0
T30	0	352	0	0
T42	0	64	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	625911	0	0
T4	5656	271	0	0
T5	238580	520	0	0
T6	850	0	0	0
T7	589356	4654	0	0
T8	783444	3614	0	0
T9	23466	0	0	0
T10	17164	0	0	0
T12	37907	0	0	0
T13	477045	0	0	0
T14	0	4858	0	0
T15	0	5775	0	0
T22	1288	48	0	0
T26	0	2505	0	0
T30	0	352	0	0
T42	0	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	625911	0	0
T4	5656	271	0	0
T5	238580	520	0	0
T6	850	0	0	0
T7	589356	4654	0	0
T8	783444	3614	0	0
T9	23466	0	0	0
T10	17164	0	0	0
T12	37907	0	0	0
T13	477045	0	0	0
T14	0	4858	0	0
T15	0	5775	0	0
T22	1288	48	0	0
T26	0	2505	0	0
T30	0	352	0	0
T42	0	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	625911	0	0
T4	5656	271	0	0
T5	238580	520	0	0
T6	850	0	0	0
T7	589356	4654	0	0
T8	783444	3614	0	0
T9	23466	0	0	0
T10	17164	0	0	0
T12	37907	0	0	0
T13	477045	0	0	0
T14	0	4858	0	0
T15	0	5775	0	0
T22	1288	48	0	0
T26	0	2505	0	0
T30	0	352	0	0
T42	0	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	28293869	0	0
T4	5656	5656	0	0
T5	238580	58600	0	0
T6	850	576	0	0
T7	589356	184024	0	0
T8	783444	84656	0	0
T9	23466	0	0	0
T10	17164	0	0	0
T12	37907	0	0	0
T13	477045	0	0	0
T14	0	160808	0	0
T22	1288	1288	0	0
T23	0	48072	0	0
T26	0	89816	0	0
T30	0	18192	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	625911	0	0
T4	5656	271	0	0
T5	238580	520	0	0
T6	850	0	0	0
T7	589356	4654	0	0
T8	783444	3614	0	0
T9	23466	0	0	0
T10	17164	0	0	0
T12	37907	0	0	0
T13	477045	0	0	0
T14	0	4858	0	0
T15	0	5775	0	0
T22	1288	48	0	0
T26	0	2505	0	0
T30	0	352	0	0
T42	0	64	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T13
1	0	Covered	T5,T7,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T5,T7,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T7,T8
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	159549102	129943425	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	159549102	858917	0	0
GntImpliesValid_A	159549102	858917	0	0
GrantKnown_A	159549102	129943425	0	0
IdxKnown_A	159549102	129943425	0	0
IndexIsCorrect_A	159549102	858917	0	0
LockArbDecision_A	159549102	0	0	0
NoReadyValidNoGrant_A	159549102	0	0	0
ReadyAndValidImplyGrant_A	159549102	858917	0	0
ReqAndReadyImplyGrant_A	159549102	858917	0	0
ReqImpliesValid_A	159549102	858917	0	0
ReqStaysHighUntilGranted0_M	159549102	0	0	0
RoundRobin_A	159549102	0	0	0
ValidKnown_A	159549102	129943425	0	0
gen_data_port_assertion.DataFlow_A	159549102	858917	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	129943425	0	0
T1	16660	16624	0	0
T2	29212	28704	0	0
T3	82509	81600	0	0
T4	5656	0	0	0
T5	238580	177713	0	0
T6	850	0	0	0
T7	589356	396307	0	0
T8	783444	692934	0	0
T9	23466	23450	0	0
T10	17164	16769	0	0
T12	0	37472	0	0
T13	0	476695	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	858917	0	0
T5	238580	1	0	0
T6	850	0	0	0
T7	589356	6752	0	0
T8	783444	3124	0	0
T9	23466	0	0	0
T10	17164	0	0	0
T12	37907	0	0	0
T13	477045	1038	0	0
T14	0	10289	0	0
T15	0	6783	0	0
T22	1288	0	0	0
T23	52026	0	0	0
T26	0	3253	0	0
T30	0	2555	0	0
T35	0	4120	0	0
T43	0	571	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	858917	0	0
T5	238580	1	0	0
T6	850	0	0	0
T7	589356	6752	0	0
T8	783444	3124	0	0
T9	23466	0	0	0
T10	17164	0	0	0
T12	37907	0	0	0
T13	477045	1038	0	0
T14	0	10289	0	0
T15	0	6783	0	0
T22	1288	0	0	0
T23	52026	0	0	0
T26	0	3253	0	0
T30	0	2555	0	0
T35	0	4120	0	0
T43	0	571	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	129943425	0	0
T1	16660	16624	0	0
T2	29212	28704	0	0
T3	82509	81600	0	0
T4	5656	0	0	0
T5	238580	177713	0	0
T6	850	0	0	0
T7	589356	396307	0	0
T8	783444	692934	0	0
T9	23466	23450	0	0
T10	17164	16769	0	0
T12	0	37472	0	0
T13	0	476695	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	129943425	0	0
T1	16660	16624	0	0
T2	29212	28704	0	0
T3	82509	81600	0	0
T4	5656	0	0	0
T5	238580	177713	0	0
T6	850	0	0	0
T7	589356	396307	0	0
T8	783444	692934	0	0
T9	23466	23450	0	0
T10	17164	16769	0	0
T12	0	37472	0	0
T13	0	476695	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	858917	0	0
T5	238580	1	0	0
T6	850	0	0	0
T7	589356	6752	0	0
T8	783444	3124	0	0
T9	23466	0	0	0
T10	17164	0	0	0
T12	37907	0	0	0
T13	477045	1038	0	0
T14	0	10289	0	0
T15	0	6783	0	0
T22	1288	0	0	0
T23	52026	0	0	0
T26	0	3253	0	0
T30	0	2555	0	0
T35	0	4120	0	0
T43	0	571	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	858917	0	0
T5	238580	1	0	0
T6	850	0	0	0
T7	589356	6752	0	0
T8	783444	3124	0	0
T9	23466	0	0	0
T10	17164	0	0	0
T12	37907	0	0	0
T13	477045	1038	0	0
T14	0	10289	0	0
T15	0	6783	0	0
T22	1288	0	0	0
T23	52026	0	0	0
T26	0	3253	0	0
T30	0	2555	0	0
T35	0	4120	0	0
T43	0	571	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	858917	0	0
T5	238580	1	0	0
T6	850	0	0	0
T7	589356	6752	0	0
T8	783444	3124	0	0
T9	23466	0	0	0
T10	17164	0	0	0
T12	37907	0	0	0
T13	477045	1038	0	0
T14	0	10289	0	0
T15	0	6783	0	0
T22	1288	0	0	0
T23	52026	0	0	0
T26	0	3253	0	0
T30	0	2555	0	0
T35	0	4120	0	0
T43	0	571	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	858917	0	0
T5	238580	1	0	0
T6	850	0	0	0
T7	589356	6752	0	0
T8	783444	3124	0	0
T9	23466	0	0	0
T10	17164	0	0	0
T12	37907	0	0	0
T13	477045	1038	0	0
T14	0	10289	0	0
T15	0	6783	0	0
T22	1288	0	0	0
T23	52026	0	0	0
T26	0	3253	0	0
T30	0	2555	0	0
T35	0	4120	0	0
T43	0	571	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	129943425	0	0
T1	16660	16624	0	0
T2	29212	28704	0	0
T3	82509	81600	0	0
T4	5656	0	0	0
T5	238580	177713	0	0
T6	850	0	0	0
T7	589356	396307	0	0
T8	783444	692934	0	0
T9	23466	23450	0	0
T10	17164	16769	0	0
T12	0	37472	0	0
T13	0	476695	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159549102	858917	0	0
T5	238580	1	0	0
T6	850	0	0	0
T7	589356	6752	0	0
T8	783444	3124	0	0
T9	23466	0	0	0
T10	17164	0	0	0
T12	37907	0	0	0
T13	477045	1038	0	0
T14	0	10289	0	0
T15	0	6783	0	0
T22	1288	0	0	0
T23	52026	0	0	0
T26	0	3253	0	0
T30	0	2555	0	0
T35	0	4120	0	0
T43	0	571	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	505598728	505513161	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	505598728	2415550	0	0
GntImpliesValid_A	505598728	2415550	0	0
GrantKnown_A	505598728	505513161	0	0
IdxKnown_A	505598728	505513161	0	0
IndexIsCorrect_A	505598728	2415550	0	0
LockArbDecision_A	505598728	0	0	0
NoReadyValidNoGrant_A	505598728	0	0	0
ReadyAndValidImplyGrant_A	505598728	2415550	0	0
ReqAndReadyImplyGrant_A	505598728	2415550	0	0
ReqImpliesValid_A	505598728	2415550	0	0
ReqStaysHighUntilGranted0_M	505598728	0	0	0
RoundRobin_A	505598728	4	0	954
ValidKnown_A	505598728	505513161	0	0
gen_data_port_assertion.DataFlow_A	505598728	2415550	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505598728	505513161	0	0
T1	41405	41354	0	0
T2	95610	95559	0	0
T3	28002	27945	0	0
T4	3338	3254	0	0
T5	130306	130215	0	0
T6	2718	2649	0	0
T7	677443	677389	0	0
T8	550770	550763	0	0
T9	27079	27014	0	0
T10	15466	15400	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505598728	2415550	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	3338	102	0	0
T5	130306	3677	0	0
T6	2718	0	0	0
T7	677443	10808	0	0
T8	550770	10469	0	0
T9	27079	832	0	0
T10	15466	1344	0	0
T22	0	33	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505598728	2415550	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	3338	102	0	0
T5	130306	3677	0	0
T6	2718	0	0	0
T7	677443	10808	0	0
T8	550770	10469	0	0
T9	27079	832	0	0
T10	15466	1344	0	0
T22	0	33	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505598728	505513161	0	0
T1	41405	41354	0	0
T2	95610	95559	0	0
T3	28002	27945	0	0
T4	3338	3254	0	0
T5	130306	130215	0	0
T6	2718	2649	0	0
T7	677443	677389	0	0
T8	550770	550763	0	0
T9	27079	27014	0	0
T10	15466	15400	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505598728	505513161	0	0
T1	41405	41354	0	0
T2	95610	95559	0	0
T3	28002	27945	0	0
T4	3338	3254	0	0
T5	130306	130215	0	0
T6	2718	2649	0	0
T7	677443	677389	0	0
T8	550770	550763	0	0
T9	27079	27014	0	0
T10	15466	15400	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505598728	2415550	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	3338	102	0	0
T5	130306	3677	0	0
T6	2718	0	0	0
T7	677443	10808	0	0
T8	550770	10469	0	0
T9	27079	832	0	0
T10	15466	1344	0	0
T22	0	33	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505598728	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505598728	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505598728	2415550	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	3338	102	0	0
T5	130306	3677	0	0
T6	2718	0	0	0
T7	677443	10808	0	0
T8	550770	10469	0	0
T9	27079	832	0	0
T10	15466	1344	0	0
T22	0	33	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505598728	2415550	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	3338	102	0	0
T5	130306	3677	0	0
T6	2718	0	0	0
T7	677443	10808	0	0
T8	550770	10469	0	0
T9	27079	832	0	0
T10	15466	1344	0	0
T22	0	33	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505598728	2415550	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	3338	102	0	0
T5	130306	3677	0	0
T6	2718	0	0	0
T7	677443	10808	0	0
T8	550770	10469	0	0
T9	27079	832	0	0
T10	15466	1344	0	0
T22	0	33	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	505598728	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505598728	4	0	954
T17	297518	1	0	1
T18	502646	0	0	1
T19	516254	0	0	1
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	7988	0	0	1
T48	28131	0	0	1
T49	277131	0	0	1
T50	25978	0	0	1
T51	15851	0	0	1
T52	118396	0	0	1
T53	747016	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505598728	505513161	0	0
T1	41405	41354	0	0
T2	95610	95559	0	0
T3	28002	27945	0	0
T4	3338	3254	0	0
T5	130306	130215	0	0
T6	2718	2649	0	0
T7	677443	677389	0	0
T8	550770	550763	0	0
T9	27079	27014	0	0
T10	15466	15400	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505598728	2415550	0	0
T1	41405	832	0	0
T2	95610	832	0	0
T3	28002	832	0	0
T4	3338	102	0	0
T5	130306	3677	0	0
T6	2718	0	0	0
T7	677443	10808	0	0
T8	550770	10469	0	0
T9	27079	832	0	0
T10	15466	1344	0	0
T22	0	33	0	0