Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	507900933	3500	0	0
addr_swap_data_rd_A	507900933	1303	0	0
addr_swap_mask_rd_A	507900933	1397	0	0
cfg_rd_A	507900933	1924	0	0
cmd_filter_0_rd_A	507900933	8897	0	0
cmd_filter_1_rd_A	507900933	10984	0	0
cmd_filter_2_rd_A	507900933	9569	0	0
cmd_filter_3_rd_A	507900933	10140	0	0
cmd_filter_4_rd_A	507900933	8594	0	0
cmd_filter_5_rd_A	507900933	10044	0	0
cmd_filter_6_rd_A	507900933	8655	0	0
cmd_filter_7_rd_A	507900933	9359	0	0
cmd_info_0_rd_A	507900933	4912	0	0
cmd_info_10_rd_A	507900933	4684	0	0
cmd_info_11_rd_A	507900933	4288	0	0
cmd_info_12_rd_A	507900933	4682	0	0
cmd_info_13_rd_A	507900933	4678	0	0
cmd_info_14_rd_A	507900933	4733	0	0
cmd_info_15_rd_A	507900933	4433	0	0
cmd_info_16_rd_A	507900933	4649	0	0
cmd_info_17_rd_A	507900933	4122	0	0
cmd_info_18_rd_A	507900933	4643	0	0
cmd_info_19_rd_A	507900933	4548	0	0
cmd_info_1_rd_A	507900933	4583	0	0
cmd_info_20_rd_A	507900933	4816	0	0
cmd_info_21_rd_A	507900933	4590	0	0
cmd_info_22_rd_A	507900933	4448	0	0
cmd_info_23_rd_A	507900933	4725	0	0
cmd_info_2_rd_A	507900933	4598	0	0
cmd_info_3_rd_A	507900933	4814	0	0
cmd_info_4_rd_A	507900933	3897	0	0
cmd_info_5_rd_A	507900933	4411	0	0
cmd_info_6_rd_A	507900933	4908	0	0
cmd_info_7_rd_A	507900933	4421	0	0
cmd_info_8_rd_A	507900933	4615	0	0
cmd_info_9_rd_A	507900933	4476	0	0
cmd_info_en4b_rd_A	507900933	1635	0	0
cmd_info_ex4b_rd_A	507900933	1727	0	0
cmd_info_wrdi_rd_A	507900933	1526	0	0
cmd_info_wren_rd_A	507900933	1690	0	0
intercept_en_rd_A	507900933	2325	0	0
intr_enable_rd_A	507900933	4089	0	0
jedec_cc_rd_A	507900933	1778	0	0
jedec_id_rd_A	507900933	1645	0	0
mailbox_addr_rd_A	507900933	1320	0	0
payload_swap_data_rd_A	507900933	1353	0	0
payload_swap_mask_rd_A	507900933	1323	0	0
read_threshold_rd_A	507900933	1436	0	0
tpm_access_0_rd_A	507900933	2280	0	0
tpm_access_1_rd_A	507900933	1407	0	0
tpm_cfg_rd_A	507900933	2280	0	0
tpm_did_vid_rd_A	507900933	1678	0	0
tpm_int_enable_rd_A	507900933	1424	0	0
tpm_int_status_rd_A	507900933	1478	0	0
tpm_int_vector_rd_A	507900933	1351	0	0
tpm_intf_capability_rd_A	507900933	1261	0	0
tpm_rid_rd_A	507900933	1198	0	0
tpm_sts_rd_A	507900933	1362	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	3500	0	0
T57	3115	96	0	0
T58	7750	73	0	0
T59	13122	4	0	0
T80	65000	3	0	0
T81	35874	1	0	0
T82	22315	321	0	0
T83	57351	3	0	0
T85	19324	282	0	0
T91	7947	3	0	0
T95	3438	9	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	1303	0	0
T59	13122	8	0	0
T80	65000	87	0	0
T81	35874	38	0	0
T82	22315	2	0	0
T126	4775	1	0	0
T127	42548	250	0	0
T128	7011	5	0	0
T129	4412	8	0	0
T130	7882	6	0	0
T131	19404	85	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	1397	0	0
T59	13122	10	0	0
T80	65000	81	0	0
T81	35874	21	0	0
T127	42548	273	0	0
T130	7882	60	0	0
T131	19404	99	0	0
T132	71823	71	0	0
T133	6237	5	0	0
T134	65741	51	0	0
T135	20487	75	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	1924	0	0
T59	13122	12	0	0
T80	65000	177	0	0
T81	35874	58	0	0
T106	6891	4	0	0
T126	4775	3	0	0
T127	42548	270	0	0
T130	7882	9	0	0
T131	19404	43	0	0
T132	71823	139	0	0
T133	6237	3	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	8897	0	0
T59	13122	93	0	0
T80	65000	1209	0	0
T81	35874	264	0	0
T126	4775	77	0	0
T127	42548	276	0	0
T128	7011	20	0	0
T129	4412	63	0	0
T130	7882	41	0	0
T131	19404	64	0	0
T132	71823	715	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	10984	0	0
T59	13122	8	0	0
T80	65000	1123	0	0
T81	35874	613	0	0
T85	19324	1	0	0
T126	4775	101	0	0
T127	42548	297	0	0
T128	7011	28	0	0
T129	4412	76	0	0
T130	7882	40	0	0
T131	19404	82	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	9569	0	0
T59	13122	95	0	0
T80	65000	1247	0	0
T81	35874	582	0	0
T126	4775	56	0	0
T127	42548	263	0	0
T128	7011	15	0	0
T129	4412	3	0	0
T130	7882	13	0	0
T131	19404	50	0	0
T132	71823	1543	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	10140	0	0
T59	13122	54	0	0
T80	65000	1609	0	0
T81	35874	405	0	0
T126	4775	6	0	0
T127	42548	261	0	0
T128	7011	8	0	0
T130	7882	19	0	0
T131	19404	67	0	0
T132	71823	1670	0	0
T133	6237	120	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	8594	0	0
T59	13122	6	0	0
T80	65000	1406	0	0
T81	35874	695	0	0
T126	4775	48	0	0
T127	42548	254	0	0
T128	7011	14	0	0
T130	7882	51	0	0
T131	19404	32	0	0
T132	71823	1021	0	0
T133	6237	5	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	10044	0	0
T59	13122	146	0	0
T80	65000	789	0	0
T81	35874	1056	0	0
T127	42548	250	0	0
T128	7011	11	0	0
T129	4412	33	0	0
T130	7882	4	0	0
T131	19404	35	0	0
T132	71823	1422	0	0
T133	6237	129	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	8655	0	0
T59	13122	10	0	0
T80	65000	1148	0	0
T81	35874	506	0	0
T126	4775	38	0	0
T127	42548	275	0	0
T128	7011	13	0	0
T129	4412	98	0	0
T130	7882	62	0	0
T131	19404	27	0	0
T132	71823	1155	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	9359	0	0
T59	13122	132	0	0
T80	65000	1217	0	0
T81	35874	519	0	0
T126	4775	57	0	0
T127	42548	317	0	0
T128	7011	27	0	0
T129	4412	57	0	0
T130	7882	9	0	0
T131	19404	82	0	0
T132	71823	1135	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4912	0	0
T59	13122	39	0	0
T80	65000	472	0	0
T81	35874	213	0	0
T126	4775	1	0	0
T127	42548	273	0	0
T128	7011	16	0	0
T130	7882	29	0	0
T131	19404	57	0	0
T132	71823	491	0	0
T133	6237	46	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4684	0	0
T59	13122	26	0	0
T80	65000	415	0	0
T81	35874	243	0	0
T126	4775	3	0	0
T127	42548	315	0	0
T128	7011	18	0	0
T129	4412	2	0	0
T130	7882	35	0	0
T131	19404	96	0	0
T132	71823	448	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4288	0	0
T59	13122	69	0	0
T80	65000	537	0	0
T81	35874	286	0	0
T127	42548	248	0	0
T128	7011	39	0	0
T129	4412	40	0	0
T130	7882	5	0	0
T131	19404	74	0	0
T132	71823	578	0	0
T133	6237	5	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4682	0	0
T59	13122	63	0	0
T80	65000	477	0	0
T81	35874	328	0	0
T127	42548	278	0	0
T128	7011	13	0	0
T129	4412	55	0	0
T130	7882	14	0	0
T131	19404	78	0	0
T132	71823	420	0	0
T133	6237	45	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4678	0	0
T59	13122	63	0	0
T80	65000	513	0	0
T81	35874	233	0	0
T127	42548	226	0	0
T128	7011	1	0	0
T129	4412	33	0	0
T130	7882	17	0	0
T131	19404	40	0	0
T132	71823	639	0	0
T133	6237	59	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4733	0	0
T59	13122	35	0	0
T80	65000	752	0	0
T81	35874	186	0	0
T82	22315	1	0	0
T126	4775	25	0	0
T127	42548	258	0	0
T128	7011	12	0	0
T129	4412	28	0	0
T130	7882	12	0	0
T131	19404	115	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4433	0	0
T59	13122	24	0	0
T80	65000	373	0	0
T81	35874	165	0	0
T126	4775	8	0	0
T127	42548	247	0	0
T128	7011	39	0	0
T130	7882	10	0	0
T131	19404	80	0	0
T132	71823	642	0	0
T133	6237	57	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4649	0	0
T59	13122	34	0	0
T80	65000	515	0	0
T81	35874	244	0	0
T126	4775	18	0	0
T127	42548	241	0	0
T128	7011	27	0	0
T130	7882	29	0	0
T131	19404	59	0	0
T132	71823	391	0	0
T133	6237	1	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4122	0	0
T59	13122	45	0	0
T80	65000	403	0	0
T81	35874	269	0	0
T126	4775	11	0	0
T127	42548	227	0	0
T128	7011	38	0	0
T129	4412	28	0	0
T130	7882	49	0	0
T131	19404	99	0	0
T132	71823	396	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4643	0	0
T59	13122	44	0	0
T80	65000	453	0	0
T81	35874	319	0	0
T126	4775	21	0	0
T127	42548	261	0	0
T128	7011	28	0	0
T129	4412	6	0	0
T130	7882	34	0	0
T131	19404	62	0	0
T132	71823	697	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4548	0	0
T59	13122	72	0	0
T80	65000	660	0	0
T81	35874	332	0	0
T106	6891	6	0	0
T126	4775	2	0	0
T127	42548	249	0	0
T130	7882	9	0	0
T131	19404	62	0	0
T132	71823	407	0	0
T133	6237	10	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4583	0	0
T59	13122	67	0	0
T80	65000	514	0	0
T81	35874	361	0	0
T126	4775	41	0	0
T127	42548	226	0	0
T128	7011	3	0	0
T129	4412	21	0	0
T130	7882	14	0	0
T131	19404	70	0	0
T132	71823	536	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4816	0	0
T59	13122	34	0	0
T80	65000	571	0	0
T81	35874	246	0	0
T126	4775	15	0	0
T127	42548	256	0	0
T128	7011	23	0	0
T129	4412	25	0	0
T130	7882	6	0	0
T131	19404	67	0	0
T132	71823	590	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4590	0	0
T59	13122	40	0	0
T80	65000	526	0	0
T81	35874	170	0	0
T126	4775	19	0	0
T127	42548	291	0	0
T128	7011	26	0	0
T129	4412	36	0	0
T130	7882	1	0	0
T131	19404	143	0	0
T132	71823	649	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4448	0	0
T59	13122	28	0	0
T80	65000	646	0	0
T81	35874	367	0	0
T126	4775	4	0	0
T127	42548	261	0	0
T128	7011	26	0	0
T129	4412	5	0	0
T130	7882	34	0	0
T131	19404	101	0	0
T132	71823	357	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4725	0	0
T59	13122	51	0	0
T80	65000	616	0	0
T81	35874	191	0	0
T126	4775	22	0	0
T127	42548	236	0	0
T128	7011	32	0	0
T129	4412	4	0	0
T130	7882	37	0	0
T131	19404	56	0	0
T132	71823	637	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4598	0	0
T59	13122	32	0	0
T80	65000	542	0	0
T81	35874	207	0	0
T126	4775	5	0	0
T127	42548	232	0	0
T128	7011	11	0	0
T129	4412	28	0	0
T130	7882	9	0	0
T131	19404	52	0	0
T132	71823	552	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4814	0	0
T59	13122	37	0	0
T80	65000	505	0	0
T81	35874	199	0	0
T85	19324	1	0	0
T126	4775	29	0	0
T127	42548	271	0	0
T128	7011	19	0	0
T129	4412	19	0	0
T130	7882	35	0	0
T131	19404	33	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	3897	0	0
T59	13122	35	0	0
T80	65000	367	0	0
T81	35874	190	0	0
T126	4775	36	0	0
T127	42548	261	0	0
T128	7011	23	0	0
T129	4412	30	0	0
T130	7882	13	0	0
T131	19404	54	0	0
T132	71823	501	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4411	0	0
T59	13122	107	0	0
T80	65000	454	0	0
T81	35874	313	0	0
T126	4775	2	0	0
T127	42548	279	0	0
T128	7011	16	0	0
T130	7882	19	0	0
T131	19404	70	0	0
T132	71823	675	0	0
T133	6237	54	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4908	0	0
T59	13122	74	0	0
T80	65000	543	0	0
T81	35874	276	0	0
T89	4315	7	0	0
T126	4775	8	0	0
T127	42548	237	0	0
T128	7011	18	0	0
T130	7882	8	0	0
T131	19404	66	0	0
T132	71823	635	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4421	0	0
T59	13122	16	0	0
T80	65000	463	0	0
T81	35874	267	0	0
T126	4775	19	0	0
T127	42548	235	0	0
T128	7011	5	0	0
T129	4412	37	0	0
T130	7882	31	0	0
T131	19404	72	0	0
T132	71823	597	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4615	0	0
T59	13122	57	0	0
T80	65000	627	0	0
T81	35874	244	0	0
T126	4775	14	0	0
T127	42548	275	0	0
T128	7011	36	0	0
T129	4412	47	0	0
T130	7882	28	0	0
T131	19404	27	0	0
T132	71823	408	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4476	0	0
T59	13122	64	0	0
T80	65000	577	0	0
T81	35874	306	0	0
T126	4775	5	0	0
T127	42548	269	0	0
T128	7011	24	0	0
T129	4412	24	0	0
T130	7882	48	0	0
T131	19404	82	0	0
T132	71823	571	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	1635	0	0
T59	13122	23	0	0
T80	65000	113	0	0
T81	35874	63	0	0
T127	42548	255	0	0
T128	7011	16	0	0
T129	4412	2	0	0
T130	7882	30	0	0
T131	19404	49	0	0
T132	71823	82	0	0
T133	6237	11	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	1727	0	0
T59	13122	23	0	0
T80	65000	100	0	0
T81	35874	55	0	0
T127	42548	236	0	0
T128	7011	36	0	0
T129	4412	5	0	0
T130	7882	41	0	0
T131	19404	44	0	0
T132	71823	111	0	0
T133	6237	8	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	1526	0	0
T59	13122	6	0	0
T80	65000	96	0	0
T81	35874	45	0	0
T126	4775	6	0	0
T127	42548	241	0	0
T128	7011	13	0	0
T129	4412	3	0	0
T130	7882	27	0	0
T131	19404	76	0	0
T132	71823	121	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	1690	0	0
T59	13122	22	0	0
T80	65000	129	0	0
T81	35874	48	0	0
T126	4775	7	0	0
T127	42548	283	0	0
T128	7011	28	0	0
T129	4412	5	0	0
T130	7882	8	0	0
T131	19404	20	0	0
T132	71823	127	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	2325	0	0
T59	13122	4	0	0
T80	65000	212	0	0
T81	35874	132	0	0
T82	22315	6	0	0
T126	4775	6	0	0
T127	42548	312	0	0
T128	7011	19	0	0
T129	4412	3	0	0
T130	7882	22	0	0
T131	19404	45	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	4089	0	0
T15	134510	22	0	0
T16	704608	51	0	0
T18	0	40	0	0
T21	0	17	0	0
T31	0	27	0	0
T40	800167	0	0	0
T69	173554	0	0	0
T70	122226	0	0	0
T112	0	43	0	0
T136	0	50	0	0
T137	0	38	0	0
T138	0	38	0	0
T139	0	7	0	0
T140	1926	0	0	0
T141	3216	0	0	0
T142	774515	0	0	0
T143	1224	0	0	0
T144	5685	0	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	1778	0	0
T59	13122	18	0	0
T80	65000	98	0	0
T81	35874	66	0	0
T82	22315	2	0	0
T126	4775	3	0	0
T127	42548	251	0	0
T128	7011	26	0	0
T130	7882	61	0	0
T131	19404	74	0	0
T132	71823	106	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	1645	0	0
T59	13122	19	0	0
T80	65000	133	0	0
T81	35874	54	0	0
T82	22315	6	0	0
T126	4775	2	0	0
T127	42548	291	0	0
T128	7011	10	0	0
T130	7882	20	0	0
T131	19404	71	0	0
T132	71823	103	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	1320	0	0
T59	13122	15	0	0
T80	65000	89	0	0
T81	35874	30	0	0
T106	6891	2	0	0
T127	42548	290	0	0
T128	7011	11	0	0
T130	7882	3	0	0
T131	19404	111	0	0
T132	71823	91	0	0
T133	6237	13	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	1353	0	0
T59	13122	14	0	0
T80	65000	91	0	0
T81	35874	49	0	0
T106	6891	4	0	0
T127	42548	249	0	0
T128	7011	15	0	0
T130	7882	8	0	0
T131	19404	53	0	0
T132	71823	71	0	0
T133	6237	3	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	1323	0	0
T59	13122	10	0	0
T80	65000	48	0	0
T81	35874	46	0	0
T85	19324	10	0	0
T127	42548	272	0	0
T128	7011	29	0	0
T129	4412	8	0	0
T130	7882	29	0	0
T131	19404	54	0	0
T132	71823	71	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	1436	0	0
T80	65000	84	0	0
T81	35874	34	0	0
T126	4775	1	0	0
T127	42548	255	0	0
T128	7011	36	0	0
T129	4412	3	0	0
T130	7882	17	0	0
T131	19404	69	0	0
T132	71823	86	0	0
T133	6237	11	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	2280	0	0
T59	13122	13	0	0
T80	65000	167	0	0
T81	35874	99	0	0
T82	22315	5	0	0
T127	42548	239	0	0
T128	7011	3	0	0
T129	4412	7	0	0
T130	7882	7	0	0
T131	19404	73	0	0
T132	71823	282	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	1407	0	0
T59	13122	3	0	0
T80	65000	69	0	0
T81	35874	48	0	0
T126	4775	8	0	0
T127	42548	254	0	0
T128	7011	37	0	0
T130	7882	23	0	0
T131	19404	91	0	0
T132	71823	64	0	0
T133	6237	5	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	2280	0	0
T59	13122	14	0	0
T80	65000	209	0	0
T81	35874	100	0	0
T126	4775	7	0	0
T127	42548	228	0	0
T128	7011	10	0	0
T129	4412	7	0	0
T130	7882	10	0	0
T131	19404	125	0	0
T132	71823	254	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	1678	0	0
T59	13122	14	0	0
T80	65000	134	0	0
T81	35874	72	0	0
T106	6891	5	0	0
T127	42548	300	0	0
T128	7011	40	0	0
T130	7882	34	0	0
T131	19404	102	0	0
T132	71823	89	0	0
T133	6237	11	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	1424	0	0
T59	13122	17	0	0
T80	65000	70	0	0
T81	35874	31	0	0
T126	4775	8	0	0
T127	42548	312	0	0
T128	7011	16	0	0
T130	7882	33	0	0
T131	19404	71	0	0
T132	71823	74	0	0
T133	6237	2	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	1478	0	0
T59	13122	13	0	0
T80	65000	59	0	0
T81	35874	27	0	0
T127	42548	259	0	0
T128	7011	34	0	0
T129	4412	1	0	0
T130	7882	34	0	0
T131	19404	101	0	0
T132	71823	97	0	0
T133	6237	5	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	1351	0	0
T59	13122	12	0	0
T80	65000	83	0	0
T81	35874	38	0	0
T85	19324	5	0	0
T127	42548	309	0	0
T128	7011	6	0	0
T130	7882	13	0	0
T131	19404	85	0	0
T132	71823	81	0	0
T133	6237	1	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	1261	0	0
T59	13122	10	0	0
T80	65000	85	0	0
T81	35874	32	0	0
T106	6891	3	0	0
T127	42548	281	0	0
T128	7011	20	0	0
T130	7882	15	0	0
T131	19404	72	0	0
T132	71823	76	0	0
T133	6237	14	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	1198	0	0
T59	13122	10	0	0
T80	65000	73	0	0
T81	35874	25	0	0
T106	6891	1	0	0
T127	42548	264	0	0
T128	7011	18	0	0
T130	7882	7	0	0
T131	19404	30	0	0
T132	71823	78	0	0
T133	6237	9	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507900933	1362	0	0
T59	13122	21	0	0
T80	65000	65	0	0
T81	35874	36	0	0
T126	4775	9	0	0
T127	42548	289	0	0
T128	7011	13	0	0
T129	4412	6	0	0
T130	7882	33	0	0
T131	19404	65	0	0
T132	71823	77	0	0