Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3515808	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4324709

1

T1

4410

T2

5039

T3

14218

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4244194	1			T1	8083		T2	8219		T3	11472
values[0x0]	1797232	1			T1	2152		T2	444		T3	6914
values[0x1]	1799091	1			T1	2199		T2	467		T3	7107

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2496274	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5344243

1

T1

6919

T2

5893

T3

17630

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30124	1			T1	62		T2	35		T3	84
valid_sources[0x01]	28318	1			T1	51		T2	54		T3	93
valid_sources[0x02]	29131	1			T1	46		T2	26		T3	93
valid_sources[0x03]	27505	1			T1	44		T2	25		T3	80
valid_sources[0x04]	37540	1			T1	41		T2	33		T3	99
valid_sources[0x05]	34980	1			T1	56		T2	18		T3	108
valid_sources[0x06]	28422	1			T1	55		T2	31		T3	91
valid_sources[0x07]	28573	1			T1	61		T2	20		T3	107
valid_sources[0x08]	33988	1			T1	64		T2	31		T3	94
valid_sources[0x09]	29352	1			T1	54		T2	28		T3	102
valid_sources[0x0a]	29158	1			T1	32		T2	30		T3	77
valid_sources[0x0b]	31509	1			T1	53		T2	30		T3	111
valid_sources[0x0c]	31131	1			T1	66		T2	28		T3	86
valid_sources[0x0d]	29538	1			T1	46		T2	34		T3	112
valid_sources[0x0e]	32125	1			T1	47		T2	32		T3	115
valid_sources[0x0f]	26647	1			T1	62		T2	34		T3	113
valid_sources[0x10]	32012	1			T1	32		T2	25		T3	82
valid_sources[0x11]	28853	1			T1	40		T2	21		T3	98
valid_sources[0x12]	30091	1			T1	41		T2	20		T3	99
valid_sources[0x13]	28530	1			T1	56		T2	28		T3	93
valid_sources[0x14]	29107	1			T1	50		T2	20		T3	95
valid_sources[0x15]	30000	1			T1	61		T2	28		T3	108
valid_sources[0x16]	36995	1			T1	57		T2	12		T3	107
valid_sources[0x17]	31418	1			T1	48		T2	21		T3	95
valid_sources[0x18]	27741	1			T1	49		T2	52		T3	94
valid_sources[0x19]	27678	1			T1	61		T2	43		T3	99
valid_sources[0x1a]	31730	1			T1	61		T2	26		T3	85
valid_sources[0x1b]	28886	1			T1	54		T2	47		T3	91
valid_sources[0x1c]	29649	1			T1	39		T2	33		T3	101
valid_sources[0x1d]	29500	1			T1	40		T2	47		T3	87
valid_sources[0x1e]	28837	1			T1	55		T2	30		T3	96
valid_sources[0x1f]	30761	1			T1	56		T2	33		T3	109
valid_sources[0x20]	28525	1			T1	52		T2	18		T3	96
valid_sources[0x21]	27180	1			T1	55		T2	23		T3	80
valid_sources[0x22]	30437	1			T1	46		T2	26		T3	88
valid_sources[0x23]	29069	1			T1	41		T2	35		T3	105
valid_sources[0x24]	30374	1			T1	45		T2	64		T3	80
valid_sources[0x25]	30137	1			T1	51		T2	34		T3	98
valid_sources[0x26]	28162	1			T1	58		T2	44		T3	98
valid_sources[0x27]	29011	1			T1	40		T2	58		T3	102
valid_sources[0x28]	29814	1			T1	46		T2	25		T3	108
valid_sources[0x29]	28699	1			T1	39		T2	21		T3	105
valid_sources[0x2a]	29293	1			T1	57		T2	45		T3	83
valid_sources[0x2b]	29057	1			T1	52		T2	47		T3	80
valid_sources[0x2c]	28137	1			T1	53		T2	34		T3	81
valid_sources[0x2d]	31247	1			T1	51		T2	56		T3	85
valid_sources[0x2e]	30225	1			T1	55		T2	26		T3	111
valid_sources[0x2f]	32215	1			T1	54		T2	23		T3	82
valid_sources[0x30]	29488	1			T1	45		T2	52		T3	112
valid_sources[0x31]	30655	1			T1	40		T2	23		T3	96
valid_sources[0x32]	29678	1			T1	43		T2	36		T3	91
valid_sources[0x33]	30917	1			T1	43		T2	38		T3	100
valid_sources[0x34]	30359	1			T1	44		T2	24		T3	113
valid_sources[0x35]	29968	1			T1	56		T2	51		T3	94
valid_sources[0x36]	29571	1			T1	50		T2	26		T3	100
valid_sources[0x37]	30197	1			T1	48		T2	81		T3	102
valid_sources[0x38]	29463	1			T1	38		T2	40		T3	101
valid_sources[0x39]	31013	1			T1	53		T2	25		T3	87
valid_sources[0x3a]	30392	1			T1	44		T2	23		T3	107
valid_sources[0x3b]	30031	1			T1	54		T2	75		T3	104
valid_sources[0x3c]	36729	1			T1	46		T2	51		T3	107
valid_sources[0x3d]	31007	1			T1	42		T2	35		T3	100
valid_sources[0x3e]	29161	1			T1	53		T2	24		T3	95
valid_sources[0x3f]	29845	1			T1	46		T2	52		T3	99
valid_sources[0x40]	63848	1			T1	50		T2	36		T3	82
valid_sources[0x41]	29648	1			T1	35		T2	62		T3	85
valid_sources[0x42]	28059	1			T1	32		T2	45		T3	87
valid_sources[0x43]	29193	1			T1	49		T2	54		T3	121
valid_sources[0x44]	33809	1			T1	62		T2	16		T3	105
valid_sources[0x45]	27807	1			T1	44		T2	39		T3	102
valid_sources[0x46]	28737	1			T1	50		T2	23		T3	107
valid_sources[0x47]	29809	1			T1	47		T2	36		T3	92
valid_sources[0x48]	28421	1			T1	54		T2	38		T3	106
valid_sources[0x49]	30246	1			T1	62		T2	13		T3	117
valid_sources[0x4a]	30846	1			T1	53		T2	43		T3	96
valid_sources[0x4b]	32469	1			T1	48		T2	40		T3	96
valid_sources[0x4c]	28503	1			T1	53		T2	62		T3	98
valid_sources[0x4d]	36253	1			T1	46		T2	34		T3	100
valid_sources[0x4e]	29004	1			T1	40		T2	15		T3	108
valid_sources[0x4f]	31458	1			T1	59		T2	17		T3	120
valid_sources[0x50]	30265	1			T1	45		T2	27		T3	108
valid_sources[0x51]	28473	1			T1	68		T2	24		T3	104
valid_sources[0x52]	31884	1			T1	49		T2	11		T3	113
valid_sources[0x53]	27984	1			T1	58		T2	24		T3	98
valid_sources[0x54]	29566	1			T1	44		T2	22		T3	94
valid_sources[0x55]	31992	1			T1	52		T2	53		T3	101
valid_sources[0x56]	30927	1			T1	64		T2	20		T3	85
valid_sources[0x57]	30946	1			T1	42		T2	58		T3	106
valid_sources[0x58]	28717	1			T1	48		T2	36		T3	101
valid_sources[0x59]	28526	1			T1	49		T2	24		T3	101
valid_sources[0x5a]	30959	1			T1	49		T2	59		T3	123
valid_sources[0x5b]	31202	1			T1	37		T2	9		T3	103
valid_sources[0x5c]	30313	1			T1	53		T2	40		T3	107
valid_sources[0x5d]	31976	1			T1	40		T2	29		T3	121
valid_sources[0x5e]	30930	1			T1	57		T2	44		T3	76
valid_sources[0x5f]	30946	1			T1	58		T2	21		T3	91
valid_sources[0x60]	32612	1			T1	47		T2	41		T3	105
valid_sources[0x61]	29008	1			T1	46		T2	51		T3	79
valid_sources[0x62]	30068	1			T1	45		T2	15		T3	111
valid_sources[0x63]	29055	1			T1	57		T2	37		T3	102
valid_sources[0x64]	27843	1			T1	72		T2	27		T3	117
valid_sources[0x65]	30229	1			T1	41		T2	45		T3	107
valid_sources[0x66]	28633	1			T1	51		T2	33		T3	116
valid_sources[0x67]	29182	1			T1	48		T2	30		T3	108
valid_sources[0x68]	30928	1			T1	51		T2	43		T3	103
valid_sources[0x69]	29751	1			T1	55		T2	56		T3	109
valid_sources[0x6a]	29296	1			T1	49		T2	36		T3	81
valid_sources[0x6b]	30396	1			T1	56		T2	62		T3	76
valid_sources[0x6c]	26982	1			T1	54		T2	49		T3	115
valid_sources[0x6d]	28113	1			T1	46		T2	27		T3	104
valid_sources[0x6e]	29992	1			T1	52		T2	46		T3	94
valid_sources[0x6f]	26611	1			T1	61		T2	22		T3	106
valid_sources[0x70]	31510	1			T1	50		T2	21		T3	112
valid_sources[0x71]	33815	1			T1	40		T2	65		T3	93
valid_sources[0x72]	29595	1			T1	45		T2	34		T3	91
valid_sources[0x73]	30341	1			T1	43		T2	28		T3	99
valid_sources[0x74]	30366	1			T1	43		T2	46		T3	105
valid_sources[0x75]	29865	1			T1	55		T2	68		T3	102
valid_sources[0x76]	40853	1			T1	54		T2	52		T3	103
valid_sources[0x77]	40479	1			T1	58		T2	33		T3	87
valid_sources[0x78]	37151	1			T1	59		T2	45		T3	94
valid_sources[0x79]	30615	1			T1	47		T2	36		T3	97
valid_sources[0x7a]	27691	1			T1	43		T2	21		T3	92
valid_sources[0x7b]	28620	1			T1	57		T2	28		T3	85
valid_sources[0x7c]	28228	1			T1	48		T2	64		T3	108
valid_sources[0x7d]	31728	1			T1	41		T2	42		T3	76
valid_sources[0x7e]	30002	1			T1	45		T2	28		T3	89
valid_sources[0x7f]	32299	1			T1	40		T2	12		T3	91
valid_sources[0x80]	30672	1			T1	36		T2	47		T3	99

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1052573

1

T1

1143

T2

4138

T3

2081

values[0x0]

all_enables

biggest_size

1647665

1

T1

1653

T2

441

T3

6059

values[0x1]

all_enables

biggest_size

1624471

1

T1

1614

T2

460

T3

6078