Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3537834

1

T1

8024

T2

4091

T3

11275

full_word

4325987

1

T1

4410

T2

5039

T3

14218

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7863391	1			T1	12434		T2	9130		T3	25493
auto[TlIntgErrCmd]	143	1			T87	11		T89	8		T90	11
auto[TlIntgErrData]	145	1			T87	13		T89	9		T90	7
auto[TlIntgErrBoth]	142	1			T87	6		T89	13		T90	12

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4247941

1

T1

8083

T2

8219

T3

11472

auto[1]

3615880

1

T1

4351

T2

911

T3

14021

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3194894	1			T1	6940		T2	4081		T3	9391
auto[TlIntgErrNone]	partial	auto[1]	342551	1			T1	1084		T2	10		T3	1884
auto[TlIntgErrNone]	full_word	auto[0]	1052858	1			T1	1143		T2	4138		T3	2081
auto[TlIntgErrNone]	full_word	auto[1]	3273088	1			T1	3267		T2	901		T3	12137
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T87	3		T89	3		T90	3
auto[TlIntgErrCmd]	partial	auto[1]	76	1			T87	6		T89	3		T90	6
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T87	2		T90	1		T164	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T89	2		T90	1		T161	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T87	4		T89	4		T90	4
auto[TlIntgErrData]	partial	auto[1]	76	1			T87	6		T89	5		T90	3
auto[TlIntgErrData]	full_word	auto[0]	8	1			T87	2		T158	1		T165	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T87	1		T166	1		T161	1
auto[TlIntgErrBoth]	partial	auto[0]	67	1			T87	4		T89	5		T90	6
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T87	2		T89	6		T90	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T89	1		T162	1		T164	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T89	1		T90	1		T162	1