Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	631414799	3457645	0	0
gen_wmask[1].MaskCheckPortA_A	631414799	3457645	0	0
gen_wmask[2].MaskCheckPortA_A	631414799	3457645	0	0
gen_wmask[3].MaskCheckPortA_A	631414799	3457645	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631414799	3457645	0	0
T1	740842	5240	0	0
T2	294658	832	0	0
T3	1560892	18491	0	0
T4	684	0	0	0
T5	628754	6416	0	0
T6	1340	0	0	0
T7	154717	832	0	0
T8	510859	0	0	0
T9	1107	0	0	0
T10	36971	1088	0	0
T12	164418	3792	0	0
T13	319564	14701	0	0
T14	27438	832	0	0
T15	0	832	0	0
T16	0	7094	0	0
T17	0	12145	0	0
T19	0	5019	0	0
T25	0	2	0	0
T26	0	12636	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631414799	3457645	0	0
T1	740842	5240	0	0
T2	294658	832	0	0
T3	1560892	18491	0	0
T4	684	0	0	0
T5	628754	6416	0	0
T6	1340	0	0	0
T7	154717	832	0	0
T8	510859	0	0	0
T9	1107	0	0	0
T10	36971	1088	0	0
T12	164418	3792	0	0
T13	319564	14701	0	0
T14	27438	832	0	0
T15	0	832	0	0
T16	0	7094	0	0
T17	0	12145	0	0
T19	0	5019	0	0
T25	0	2	0	0
T26	0	12636	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631414799	3457645	0	0
T1	740842	5240	0	0
T2	294658	832	0	0
T3	1560892	18491	0	0
T4	684	0	0	0
T5	628754	6416	0	0
T6	1340	0	0	0
T7	154717	832	0	0
T8	510859	0	0	0
T9	1107	0	0	0
T10	36971	1088	0	0
T12	164418	3792	0	0
T13	319564	14701	0	0
T14	27438	832	0	0
T15	0	832	0	0
T16	0	7094	0	0
T17	0	12145	0	0
T19	0	5019	0	0
T25	0	2	0	0
T26	0	12636	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631414799	3457645	0	0
T1	740842	5240	0	0
T2	294658	832	0	0
T3	1560892	18491	0	0
T4	684	0	0	0
T5	628754	6416	0	0
T6	1340	0	0	0
T7	154717	832	0	0
T8	510859	0	0	0
T9	1107	0	0	0
T10	36971	1088	0	0
T12	164418	3792	0	0
T13	319564	14701	0	0
T14	27438	832	0	0
T15	0	832	0	0
T16	0	7094	0	0
T17	0	12145	0	0
T19	0	5019	0	0
T25	0	2	0	0
T26	0	12636	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	474758817	2174172	0	0
gen_wmask[1].MaskCheckPortA_A	474758817	2174172	0	0
gen_wmask[2].MaskCheckPortA_A	474758817	2174172	0	0
gen_wmask[3].MaskCheckPortA_A	474758817	2174172	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474758817	2174172	0	0
T1	601294	1756	0	0
T2	258278	832	0	0
T3	799340	7923	0	0
T4	684	0	0	0
T5	148075	4992	0	0
T6	1340	0	0	0
T7	133075	832	0	0
T8	410689	0	0	0
T9	1107	0	0	0
T10	31739	1088	0	0
T12	0	832	0	0
T13	0	8320	0	0
T14	0	832	0	0
T15	0	832	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474758817	2174172	0	0
T1	601294	1756	0	0
T2	258278	832	0	0
T3	799340	7923	0	0
T4	684	0	0	0
T5	148075	4992	0	0
T6	1340	0	0	0
T7	133075	832	0	0
T8	410689	0	0	0
T9	1107	0	0	0
T10	31739	1088	0	0
T12	0	832	0	0
T13	0	8320	0	0
T14	0	832	0	0
T15	0	832	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474758817	2174172	0	0
T1	601294	1756	0	0
T2	258278	832	0	0
T3	799340	7923	0	0
T4	684	0	0	0
T5	148075	4992	0	0
T6	1340	0	0	0
T7	133075	832	0	0
T8	410689	0	0	0
T9	1107	0	0	0
T10	31739	1088	0	0
T12	0	832	0	0
T13	0	8320	0	0
T14	0	832	0	0
T15	0	832	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474758817	2174172	0	0
T1	601294	1756	0	0
T2	258278	832	0	0
T3	799340	7923	0	0
T4	684	0	0	0
T5	148075	4992	0	0
T6	1340	0	0	0
T7	133075	832	0	0
T8	410689	0	0	0
T9	1107	0	0	0
T10	31739	1088	0	0
T12	0	832	0	0
T13	0	8320	0	0
T14	0	832	0	0
T15	0	832	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	156655982	1283473	0	0
gen_wmask[1].MaskCheckPortA_A	156655982	1283473	0	0
gen_wmask[2].MaskCheckPortA_A	156655982	1283473	0	0
gen_wmask[3].MaskCheckPortA_A	156655982	1283473	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	1283473	0	0
T1	139548	3484	0	0
T2	36380	0	0	0
T3	761552	10568	0	0
T5	480679	1424	0	0
T7	21642	0	0	0
T8	100170	0	0	0
T10	5232	0	0	0
T12	164418	2960	0	0
T13	319564	6381	0	0
T14	27438	0	0	0
T16	0	7094	0	0
T17	0	12145	0	0
T19	0	5019	0	0
T25	0	2	0	0
T26	0	12636	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	1283473	0	0
T1	139548	3484	0	0
T2	36380	0	0	0
T3	761552	10568	0	0
T5	480679	1424	0	0
T7	21642	0	0	0
T8	100170	0	0	0
T10	5232	0	0	0
T12	164418	2960	0	0
T13	319564	6381	0	0
T14	27438	0	0	0
T16	0	7094	0	0
T17	0	12145	0	0
T19	0	5019	0	0
T25	0	2	0	0
T26	0	12636	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	1283473	0	0
T1	139548	3484	0	0
T2	36380	0	0	0
T3	761552	10568	0	0
T5	480679	1424	0	0
T7	21642	0	0	0
T8	100170	0	0	0
T10	5232	0	0	0
T12	164418	2960	0	0
T13	319564	6381	0	0
T14	27438	0	0	0
T16	0	7094	0	0
T17	0	12145	0	0
T19	0	5019	0	0
T25	0	2	0	0
T26	0	12636	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	1283473	0	0
T1	139548	3484	0	0
T2	36380	0	0	0
T3	761552	10568	0	0
T5	480679	1424	0	0
T7	21642	0	0	0
T8	100170	0	0	0
T10	5232	0	0	0
T12	164418	2960	0	0
T13	319564	6381	0	0
T14	27438	0	0	0
T16	0	7094	0	0
T17	0	12145	0	0
T19	0	5019	0	0
T25	0	2	0	0
T26	0	12636	0	0