Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476785012	3034505	0	0
DepthKnown_A	476785012	476651089	0	0
RvalidKnown_A	476785012	476651089	0	0
WreadyKnown_A	476785012	476651089	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	3034505	0	0
T2	258278	1663	0	0
T3	799340	11642	0	0
T4	684	0	0	0
T5	148075	7485	0	0
T6	1340	0	0	0
T7	133075	1663	0	0
T8	410689	0	0	0
T9	1107	0	0	0
T10	31739	1343	0	0
T11	5116	0	0	0
T12	0	832	0	0
T13	0	10813	0	0
T14	0	1663	0	0
T15	0	832	0	0
T16	0	13306	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	476651089	0	0
T1	601294	601229	0	0
T2	258278	258180	0	0
T3	799340	799270	0	0
T4	684	634	0	0
T5	148075	148066	0	0
T6	1340	1283	0	0
T7	133075	132975	0	0
T8	410689	410638	0	0
T9	1107	1007	0	0
T10	31739	31677	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	476651089	0	0
T1	601294	601229	0	0
T2	258278	258180	0	0
T3	799340	799270	0	0
T4	684	634	0	0
T5	148075	148066	0	0
T6	1340	1283	0	0
T7	133075	132975	0	0
T8	410689	410638	0	0
T9	1107	1007	0	0
T10	31739	31677	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	476651089	0	0
T1	601294	601229	0	0
T2	258278	258180	0	0
T3	799340	799270	0	0
T4	684	634	0	0
T5	148075	148066	0	0
T6	1340	1283	0	0
T7	133075	132975	0	0
T8	410689	410638	0	0
T9	1107	1007	0	0
T10	31739	31677	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476785012	3306768	0	0
DepthKnown_A	476785012	476651089	0	0
RvalidKnown_A	476785012	476651089	0	0
WreadyKnown_A	476785012	476651089	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	3306768	0	0
T2	258278	832	0	0
T3	799340	6656	0	0
T4	684	0	0	0
T5	148075	4992	0	0
T6	1340	0	0	0
T7	133075	832	0	0
T8	410689	0	0	0
T9	1107	0	0	0
T10	31739	3990	0	0
T11	5116	0	0	0
T12	0	832	0	0
T13	0	8320	0	0
T14	0	832	0	0
T15	0	3648	0	0
T16	0	8320	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	476651089	0	0
T1	601294	601229	0	0
T2	258278	258180	0	0
T3	799340	799270	0	0
T4	684	634	0	0
T5	148075	148066	0	0
T6	1340	1283	0	0
T7	133075	132975	0	0
T8	410689	410638	0	0
T9	1107	1007	0	0
T10	31739	31677	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	476651089	0	0
T1	601294	601229	0	0
T2	258278	258180	0	0
T3	799340	799270	0	0
T4	684	634	0	0
T5	148075	148066	0	0
T6	1340	1283	0	0
T7	133075	132975	0	0
T8	410689	410638	0	0
T9	1107	1007	0	0
T10	31739	31677	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	476651089	0	0
T1	601294	601229	0	0
T2	258278	258180	0	0
T3	799340	799270	0	0
T4	684	634	0	0
T5	148075	148066	0	0
T6	1340	1283	0	0
T7	133075	132975	0	0
T8	410689	410638	0	0
T9	1107	1007	0	0
T10	31739	31677	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476785012	184121	0	0
DepthKnown_A	476785012	476651089	0	0
RvalidKnown_A	476785012	476651089	0	0
WreadyKnown_A	476785012	476651089	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	184121	0	0
T1	601294	901	0	0
T2	258278	0	0	0
T3	799340	1340	0	0
T4	684	0	0	0
T5	148075	288	0	0
T6	1340	0	0	0
T7	133075	0	0	0
T8	410689	0	0	0
T9	1107	0	0	0
T10	31739	0	0	0
T12	0	128	0	0
T13	0	517	0	0
T16	0	640	0	0
T17	0	1690	0	0
T19	0	1148	0	0
T26	0	1142	0	0
T34	0	256	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	476651089	0	0
T1	601294	601229	0	0
T2	258278	258180	0	0
T3	799340	799270	0	0
T4	684	634	0	0
T5	148075	148066	0	0
T6	1340	1283	0	0
T7	133075	132975	0	0
T8	410689	410638	0	0
T9	1107	1007	0	0
T10	31739	31677	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	476651089	0	0
T1	601294	601229	0	0
T2	258278	258180	0	0
T3	799340	799270	0	0
T4	684	634	0	0
T5	148075	148066	0	0
T6	1340	1283	0	0
T7	133075	132975	0	0
T8	410689	410638	0	0
T9	1107	1007	0	0
T10	31739	31677	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	476651089	0	0
T1	601294	601229	0	0
T2	258278	258180	0	0
T3	799340	799270	0	0
T4	684	634	0	0
T5	148075	148066	0	0
T6	1340	1283	0	0
T7	133075	132975	0	0
T8	410689	410638	0	0
T9	1107	1007	0	0
T10	31739	31677	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476785012	448303	0	0
DepthKnown_A	476785012	476651089	0	0
RvalidKnown_A	476785012	476651089	0	0
WreadyKnown_A	476785012	476651089	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	448303	0	0
T1	601294	901	0	0
T2	258278	0	0	0
T3	799340	1336	0	0
T4	684	0	0	0
T5	148075	288	0	0
T6	1340	0	0	0
T7	133075	0	0	0
T8	410689	0	0	0
T9	1107	0	0	0
T10	31739	0	0	0
T12	0	128	0	0
T13	0	517	0	0
T16	0	640	0	0
T17	0	1689	0	0
T19	0	5237	0	0
T26	0	1130	0	0
T34	0	256	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	476651089	0	0
T1	601294	601229	0	0
T2	258278	258180	0	0
T3	799340	799270	0	0
T4	684	634	0	0
T5	148075	148066	0	0
T6	1340	1283	0	0
T7	133075	132975	0	0
T8	410689	410638	0	0
T9	1107	1007	0	0
T10	31739	31677	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	476651089	0	0
T1	601294	601229	0	0
T2	258278	258180	0	0
T3	799340	799270	0	0
T4	684	634	0	0
T5	148075	148066	0	0
T6	1340	1283	0	0
T7	133075	132975	0	0
T8	410689	410638	0	0
T9	1107	1007	0	0
T10	31739	31677	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	476651089	0	0
T1	601294	601229	0	0
T2	258278	258180	0	0
T3	799340	799270	0	0
T4	684	634	0	0
T5	148075	148066	0	0
T6	1340	1283	0	0
T7	133075	132975	0	0
T8	410689	410638	0	0
T9	1107	1007	0	0
T10	31739	31677	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476785012	6148489	0	0
DepthKnown_A	476785012	476651089	0	0
RvalidKnown_A	476785012	476651089	0	0
WreadyKnown_A	476785012	476651089	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	6148489	0	0
T1	601294	11563	0	0
T2	258278	8298	0	0
T3	799340	17625	0	0
T4	684	2	0	0
T5	148075	2486	0	0
T6	1340	16	0	0
T7	133075	4328	0	0
T8	410689	785	0	0
T9	1107	19	0	0
T10	31739	857	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	476651089	0	0
T1	601294	601229	0	0
T2	258278	258180	0	0
T3	799340	799270	0	0
T4	684	634	0	0
T5	148075	148066	0	0
T6	1340	1283	0	0
T7	133075	132975	0	0
T8	410689	410638	0	0
T9	1107	1007	0	0
T10	31739	31677	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	476651089	0	0
T1	601294	601229	0	0
T2	258278	258180	0	0
T3	799340	799270	0	0
T4	684	634	0	0
T5	148075	148066	0	0
T6	1340	1283	0	0
T7	133075	132975	0	0
T8	410689	410638	0	0
T9	1107	1007	0	0
T10	31739	31677	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	476651089	0	0
T1	601294	601229	0	0
T2	258278	258180	0	0
T3	799340	799270	0	0
T4	684	634	0	0
T5	148075	148066	0	0
T6	1340	1283	0	0
T7	133075	132975	0	0
T8	410689	410638	0	0
T9	1107	1007	0	0
T10	31739	31677	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476785012	13813276	0	0
DepthKnown_A	476785012	476651089	0	0
RvalidKnown_A	476785012	476651089	0	0
WreadyKnown_A	476785012	476651089	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	13813276	0	0
T1	601294	11533	0	0
T2	258278	36287	0	0
T3	799340	17501	0	0
T4	684	2	0	0
T5	148075	2486	0	0
T6	1340	72	0	0
T7	133075	4328	0	0
T8	410689	785	0	0
T9	1107	19	0	0
T10	31739	3677	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	476651089	0	0
T1	601294	601229	0	0
T2	258278	258180	0	0
T3	799340	799270	0	0
T4	684	634	0	0
T5	148075	148066	0	0
T6	1340	1283	0	0
T7	133075	132975	0	0
T8	410689	410638	0	0
T9	1107	1007	0	0
T10	31739	31677	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	476651089	0	0
T1	601294	601229	0	0
T2	258278	258180	0	0
T3	799340	799270	0	0
T4	684	634	0	0
T5	148075	148066	0	0
T6	1340	1283	0	0
T7	133075	132975	0	0
T8	410689	410638	0	0
T9	1107	1007	0	0
T10	31739	31677	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	476651089	0	0
T1	601294	601229	0	0
T2	258278	258180	0	0
T3	799340	799270	0	0
T4	684	634	0	0
T5	148075	148066	0	0
T6	1340	1283	0	0
T7	133075	132975	0	0
T8	410689	410638	0	0
T9	1107	1007	0	0
T10	31739	31677	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0