Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T16
1	0	Covered	T1,T3,T16

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Unreachable
1	1	Covered	T1,T3,T16

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T12
1	0	Covered	T3,T5,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Unreachable
1	1	Covered	T3,T5,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	788070781	629979427	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	788070781	3828929	0	0
GntImpliesValid_A	788070781	3828929	0	0
GrantKnown_A	788070781	629979427	0	0
IdxKnown_A	788070781	629979427	0	0
IndexIsCorrect_A	788070781	3828929	0	0
LockArbDecision_A	788070781	0	0	0
NoReadyValidNoGrant_A	788070781	0	0	0
ReadyAndValidImplyGrant_A	788070781	3828929	0	0
ReqAndReadyImplyGrant_A	788070781	3828929	0	0
ReqImpliesValid_A	788070781	3828929	0	0
ReqStaysHighUntilGranted0_M	788070781	0	0	0
RoundRobin_A	788070781	9	0	956
ValidKnown_A	788070781	629979427	0	0
gen_data_port_assertion.DataFlow_A	788070781	3828929	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788070781	629979427	0	0
T1	740842	735269	0	0
T2	331038	294560	0	0
T3	2322444	1553635	0	0
T4	684	634	0	0
T5	1109433	627770	0	0
T6	1340	1283	0	0
T7	176359	154617	0	0
T8	611029	507014	0	0
T9	1107	1007	0	0
T10	42203	36909	0	0
T12	328836	163772	0	0
T13	639128	318556	0	0
T14	54876	26910	0	0
T15	100076	99694	0	0
T16	0	430485	0	0
T17	0	206280	0	0
T19	0	214560	0	0
T20	0	139688	0	0
T26	0	285688	0	0
T28	0	108120	0	0
T29	0	576	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788070781	3828929	0	0
T1	740842	8089	0	0
T2	294658	832	0	0
T3	2322444	21216	0	0
T4	684	0	0	0
T5	1109433	6718	0	0
T6	1340	0	0	0
T7	176359	832	0	0
T8	611029	0	0	0
T9	1107	0	0	0
T10	42203	1088	0	0
T12	328836	3924	0	0
T13	639128	15257	0	0
T14	54876	832	0	0
T15	100076	832	0	0
T16	432882	7269	0	0
T17	0	13807	0	0
T19	0	6512	0	0
T20	0	6087	0	0
T21	0	241	0	0
T25	0	2	0	0
T26	0	13628	0	0
T34	0	3190	0	0
T37	0	4592	0	0
T44	0	4249	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788070781	3828929	0	0
T1	740842	8089	0	0
T2	294658	832	0	0
T3	2322444	21216	0	0
T4	684	0	0	0
T5	1109433	6718	0	0
T6	1340	0	0	0
T7	176359	832	0	0
T8	611029	0	0	0
T9	1107	0	0	0
T10	42203	1088	0	0
T12	328836	3924	0	0
T13	639128	15257	0	0
T14	54876	832	0	0
T15	100076	832	0	0
T16	432882	7269	0	0
T17	0	13807	0	0
T19	0	6512	0	0
T20	0	6087	0	0
T21	0	241	0	0
T25	0	2	0	0
T26	0	13628	0	0
T34	0	3190	0	0
T37	0	4592	0	0
T44	0	4249	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788070781	629979427	0	0
T1	740842	735269	0	0
T2	331038	294560	0	0
T3	2322444	1553635	0	0
T4	684	634	0	0
T5	1109433	627770	0	0
T6	1340	1283	0	0
T7	176359	154617	0	0
T8	611029	507014	0	0
T9	1107	1007	0	0
T10	42203	36909	0	0
T12	328836	163772	0	0
T13	639128	318556	0	0
T14	54876	26910	0	0
T15	100076	99694	0	0
T16	0	430485	0	0
T17	0	206280	0	0
T19	0	214560	0	0
T20	0	139688	0	0
T26	0	285688	0	0
T28	0	108120	0	0
T29	0	576	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788070781	629979427	0	0
T1	740842	735269	0	0
T2	331038	294560	0	0
T3	2322444	1553635	0	0
T4	684	634	0	0
T5	1109433	627770	0	0
T6	1340	1283	0	0
T7	176359	154617	0	0
T8	611029	507014	0	0
T9	1107	1007	0	0
T10	42203	36909	0	0
T12	328836	163772	0	0
T13	639128	318556	0	0
T14	54876	26910	0	0
T15	100076	99694	0	0
T16	0	430485	0	0
T17	0	206280	0	0
T19	0	214560	0	0
T20	0	139688	0	0
T26	0	285688	0	0
T28	0	108120	0	0
T29	0	576	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788070781	3828929	0	0
T1	740842	8089	0	0
T2	294658	832	0	0
T3	2322444	21216	0	0
T4	684	0	0	0
T5	1109433	6718	0	0
T6	1340	0	0	0
T7	176359	832	0	0
T8	611029	0	0	0
T9	1107	0	0	0
T10	42203	1088	0	0
T12	328836	3924	0	0
T13	639128	15257	0	0
T14	54876	832	0	0
T15	100076	832	0	0
T16	432882	7269	0	0
T17	0	13807	0	0
T19	0	6512	0	0
T20	0	6087	0	0
T21	0	241	0	0
T25	0	2	0	0
T26	0	13628	0	0
T34	0	3190	0	0
T37	0	4592	0	0
T44	0	4249	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788070781	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788070781	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788070781	3828929	0	0
T1	740842	8089	0	0
T2	294658	832	0	0
T3	2322444	21216	0	0
T4	684	0	0	0
T5	1109433	6718	0	0
T6	1340	0	0	0
T7	176359	832	0	0
T8	611029	0	0	0
T9	1107	0	0	0
T10	42203	1088	0	0
T12	328836	3924	0	0
T13	639128	15257	0	0
T14	54876	832	0	0
T15	100076	832	0	0
T16	432882	7269	0	0
T17	0	13807	0	0
T19	0	6512	0	0
T20	0	6087	0	0
T21	0	241	0	0
T25	0	2	0	0
T26	0	13628	0	0
T34	0	3190	0	0
T37	0	4592	0	0
T44	0	4249	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788070781	3828929	0	0
T1	740842	8089	0	0
T2	294658	832	0	0
T3	2322444	21216	0	0
T4	684	0	0	0
T5	1109433	6718	0	0
T6	1340	0	0	0
T7	176359	832	0	0
T8	611029	0	0	0
T9	1107	0	0	0
T10	42203	1088	0	0
T12	328836	3924	0	0
T13	639128	15257	0	0
T14	54876	832	0	0
T15	100076	832	0	0
T16	432882	7269	0	0
T17	0	13807	0	0
T19	0	6512	0	0
T20	0	6087	0	0
T21	0	241	0	0
T25	0	2	0	0
T26	0	13628	0	0
T34	0	3190	0	0
T37	0	4592	0	0
T44	0	4249	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788070781	3828929	0	0
T1	740842	8089	0	0
T2	294658	832	0	0
T3	2322444	21216	0	0
T4	684	0	0	0
T5	1109433	6718	0	0
T6	1340	0	0	0
T7	176359	832	0	0
T8	611029	0	0	0
T9	1107	0	0	0
T10	42203	1088	0	0
T12	328836	3924	0	0
T13	639128	15257	0	0
T14	54876	832	0	0
T15	100076	832	0	0
T16	432882	7269	0	0
T17	0	13807	0	0
T19	0	6512	0	0
T20	0	6087	0	0
T21	0	241	0	0
T25	0	2	0	0
T26	0	13628	0	0
T34	0	3190	0	0
T37	0	4592	0	0
T44	0	4249	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	788070781	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788070781	9	0	956
T24	566912	1	0	1
T30	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	888528	0	0	1
T52	7721	0	0	1
T53	2718	0	0	1
T54	183757	0	0	1
T55	181398	0	0	1
T56	13076	0	0	1
T57	4009	0	0	1
T58	1045	0	0	1
T59	523337	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788070781	629979427	0	0
T1	740842	735269	0	0
T2	331038	294560	0	0
T3	2322444	1553635	0	0
T4	684	634	0	0
T5	1109433	627770	0	0
T6	1340	1283	0	0
T7	176359	154617	0	0
T8	611029	507014	0	0
T9	1107	1007	0	0
T10	42203	36909	0	0
T12	328836	163772	0	0
T13	639128	318556	0	0
T14	54876	26910	0	0
T15	100076	99694	0	0
T16	0	430485	0	0
T17	0	206280	0	0
T19	0	214560	0	0
T20	0	139688	0	0
T26	0	285688	0	0
T28	0	108120	0	0
T29	0	576	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788070781	3828929	0	0
T1	740842	8089	0	0
T2	294658	832	0	0
T3	2322444	21216	0	0
T4	684	0	0	0
T5	1109433	6718	0	0
T6	1340	0	0	0
T7	176359	832	0	0
T8	611029	0	0	0
T9	1107	0	0	0
T10	42203	1088	0	0
T12	328836	3924	0	0
T13	639128	15257	0	0
T14	54876	832	0	0
T15	100076	832	0	0
T16	432882	7269	0	0
T17	0	13807	0	0
T19	0	6512	0	0
T20	0	6087	0	0
T21	0	241	0	0
T25	0	2	0	0
T26	0	13628	0	0
T34	0	3190	0	0
T37	0	4592	0	0
T44	0	4249	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T16
1	0	Covered	T1,T3,T16

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Unreachable
1	1	Covered	T1,T3,T16

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T16
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T8

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	156655982	26560606	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	156655982	600074	0	0
GntImpliesValid_A	156655982	600074	0	0
GrantKnown_A	156655982	26560606	0	0
IdxKnown_A	156655982	26560606	0	0
IndexIsCorrect_A	156655982	600074	0	0
LockArbDecision_A	156655982	0	0	0
NoReadyValidNoGrant_A	156655982	0	0	0
ReadyAndValidImplyGrant_A	156655982	600074	0	0
ReqAndReadyImplyGrant_A	156655982	600074	0	0
ReqImpliesValid_A	156655982	600074	0	0
ReqStaysHighUntilGranted0_M	156655982	0	0	0
RoundRobin_A	156655982	0	0	0
ValidKnown_A	156655982	26560606	0	0
gen_data_port_assertion.DataFlow_A	156655982	600074	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	26560606	0	0
T1	139548	134040	0	0
T2	36380	0	0	0
T3	761552	199832	0	0
T5	480679	0	0	0
T7	21642	0	0	0
T8	100170	96376	0	0
T10	5232	0	0	0
T12	164418	0	0	0
T13	319564	0	0	0
T14	27438	0	0	0
T16	0	32560	0	0
T17	0	206280	0	0
T19	0	214560	0	0
T20	0	139688	0	0
T26	0	285688	0	0
T28	0	108120	0	0
T29	0	576	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	600074	0	0
T1	139548	5432	0	0
T2	36380	0	0	0
T3	761552	5271	0	0
T5	480679	0	0	0
T7	21642	0	0	0
T8	100170	0	0	0
T10	5232	0	0	0
T12	164418	0	0	0
T13	319564	0	0	0
T14	27438	0	0	0
T16	0	917	0	0
T17	0	5270	0	0
T19	0	4502	0	0
T20	0	6087	0	0
T21	0	241	0	0
T26	0	2624	0	0
T37	0	4592	0	0
T44	0	4249	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	600074	0	0
T1	139548	5432	0	0
T2	36380	0	0	0
T3	761552	5271	0	0
T5	480679	0	0	0
T7	21642	0	0	0
T8	100170	0	0	0
T10	5232	0	0	0
T12	164418	0	0	0
T13	319564	0	0	0
T14	27438	0	0	0
T16	0	917	0	0
T17	0	5270	0	0
T19	0	4502	0	0
T20	0	6087	0	0
T21	0	241	0	0
T26	0	2624	0	0
T37	0	4592	0	0
T44	0	4249	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	26560606	0	0
T1	139548	134040	0	0
T2	36380	0	0	0
T3	761552	199832	0	0
T5	480679	0	0	0
T7	21642	0	0	0
T8	100170	96376	0	0
T10	5232	0	0	0
T12	164418	0	0	0
T13	319564	0	0	0
T14	27438	0	0	0
T16	0	32560	0	0
T17	0	206280	0	0
T19	0	214560	0	0
T20	0	139688	0	0
T26	0	285688	0	0
T28	0	108120	0	0
T29	0	576	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	26560606	0	0
T1	139548	134040	0	0
T2	36380	0	0	0
T3	761552	199832	0	0
T5	480679	0	0	0
T7	21642	0	0	0
T8	100170	96376	0	0
T10	5232	0	0	0
T12	164418	0	0	0
T13	319564	0	0	0
T14	27438	0	0	0
T16	0	32560	0	0
T17	0	206280	0	0
T19	0	214560	0	0
T20	0	139688	0	0
T26	0	285688	0	0
T28	0	108120	0	0
T29	0	576	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	600074	0	0
T1	139548	5432	0	0
T2	36380	0	0	0
T3	761552	5271	0	0
T5	480679	0	0	0
T7	21642	0	0	0
T8	100170	0	0	0
T10	5232	0	0	0
T12	164418	0	0	0
T13	319564	0	0	0
T14	27438	0	0	0
T16	0	917	0	0
T17	0	5270	0	0
T19	0	4502	0	0
T20	0	6087	0	0
T21	0	241	0	0
T26	0	2624	0	0
T37	0	4592	0	0
T44	0	4249	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	600074	0	0
T1	139548	5432	0	0
T2	36380	0	0	0
T3	761552	5271	0	0
T5	480679	0	0	0
T7	21642	0	0	0
T8	100170	0	0	0
T10	5232	0	0	0
T12	164418	0	0	0
T13	319564	0	0	0
T14	27438	0	0	0
T16	0	917	0	0
T17	0	5270	0	0
T19	0	4502	0	0
T20	0	6087	0	0
T21	0	241	0	0
T26	0	2624	0	0
T37	0	4592	0	0
T44	0	4249	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	600074	0	0
T1	139548	5432	0	0
T2	36380	0	0	0
T3	761552	5271	0	0
T5	480679	0	0	0
T7	21642	0	0	0
T8	100170	0	0	0
T10	5232	0	0	0
T12	164418	0	0	0
T13	319564	0	0	0
T14	27438	0	0	0
T16	0	917	0	0
T17	0	5270	0	0
T19	0	4502	0	0
T20	0	6087	0	0
T21	0	241	0	0
T26	0	2624	0	0
T37	0	4592	0	0
T44	0	4249	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	600074	0	0
T1	139548	5432	0	0
T2	36380	0	0	0
T3	761552	5271	0	0
T5	480679	0	0	0
T7	21642	0	0	0
T8	100170	0	0	0
T10	5232	0	0	0
T12	164418	0	0	0
T13	319564	0	0	0
T14	27438	0	0	0
T16	0	917	0	0
T17	0	5270	0	0
T19	0	4502	0	0
T20	0	6087	0	0
T21	0	241	0	0
T26	0	2624	0	0
T37	0	4592	0	0
T44	0	4249	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	26560606	0	0
T1	139548	134040	0	0
T2	36380	0	0	0
T3	761552	199832	0	0
T5	480679	0	0	0
T7	21642	0	0	0
T8	100170	96376	0	0
T10	5232	0	0	0
T12	164418	0	0	0
T13	319564	0	0	0
T14	27438	0	0	0
T16	0	32560	0	0
T17	0	206280	0	0
T19	0	214560	0	0
T20	0	139688	0	0
T26	0	285688	0	0
T28	0	108120	0	0
T29	0	576	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	600074	0	0
T1	139548	5432	0	0
T2	36380	0	0	0
T3	761552	5271	0	0
T5	480679	0	0	0
T7	21642	0	0	0
T8	100170	0	0	0
T10	5232	0	0	0
T12	164418	0	0	0
T13	319564	0	0	0
T14	27438	0	0	0
T16	0	917	0	0
T17	0	5270	0	0
T19	0	4502	0	0
T20	0	6087	0	0
T21	0	241	0	0
T26	0	2624	0	0
T37	0	4592	0	0
T44	0	4249	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T12
1	0	Covered	T3,T5,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Unreachable
1	1	Covered	T3,T5,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T5,T12
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	156655982	128746256	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	156655982	877121	0	0
GntImpliesValid_A	156655982	877121	0	0
GrantKnown_A	156655982	128746256	0	0
IdxKnown_A	156655982	128746256	0	0
IndexIsCorrect_A	156655982	877121	0	0
LockArbDecision_A	156655982	0	0	0
NoReadyValidNoGrant_A	156655982	0	0	0
ReadyAndValidImplyGrant_A	156655982	877121	0	0
ReqAndReadyImplyGrant_A	156655982	877121	0	0
ReqImpliesValid_A	156655982	877121	0	0
ReqStaysHighUntilGranted0_M	156655982	0	0	0
RoundRobin_A	156655982	0	0	0
ValidKnown_A	156655982	128746256	0	0
gen_data_port_assertion.DataFlow_A	156655982	877121	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	128746256	0	0
T2	36380	36380	0	0
T3	761552	554533	0	0
T5	480679	479704	0	0
T7	21642	21642	0	0
T8	100170	0	0	0
T10	5232	5232	0	0
T12	164418	163772	0	0
T13	319564	318556	0	0
T14	27438	26910	0	0
T15	100076	99694	0	0
T16	0	397925	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	877121	0	0
T3	761552	6665	0	0
T5	480679	1424	0	0
T7	21642	0	0	0
T8	100170	0	0	0
T10	5232	0	0	0
T12	164418	2960	0	0
T13	319564	6381	0	0
T14	27438	0	0	0
T15	100076	0	0	0
T16	432882	6352	0	0
T17	0	8537	0	0
T19	0	2010	0	0
T25	0	2	0	0
T26	0	11004	0	0
T34	0	3190	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	877121	0	0
T3	761552	6665	0	0
T5	480679	1424	0	0
T7	21642	0	0	0
T8	100170	0	0	0
T10	5232	0	0	0
T12	164418	2960	0	0
T13	319564	6381	0	0
T14	27438	0	0	0
T15	100076	0	0	0
T16	432882	6352	0	0
T17	0	8537	0	0
T19	0	2010	0	0
T25	0	2	0	0
T26	0	11004	0	0
T34	0	3190	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	128746256	0	0
T2	36380	36380	0	0
T3	761552	554533	0	0
T5	480679	479704	0	0
T7	21642	21642	0	0
T8	100170	0	0	0
T10	5232	5232	0	0
T12	164418	163772	0	0
T13	319564	318556	0	0
T14	27438	26910	0	0
T15	100076	99694	0	0
T16	0	397925	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	128746256	0	0
T2	36380	36380	0	0
T3	761552	554533	0	0
T5	480679	479704	0	0
T7	21642	21642	0	0
T8	100170	0	0	0
T10	5232	5232	0	0
T12	164418	163772	0	0
T13	319564	318556	0	0
T14	27438	26910	0	0
T15	100076	99694	0	0
T16	0	397925	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	877121	0	0
T3	761552	6665	0	0
T5	480679	1424	0	0
T7	21642	0	0	0
T8	100170	0	0	0
T10	5232	0	0	0
T12	164418	2960	0	0
T13	319564	6381	0	0
T14	27438	0	0	0
T15	100076	0	0	0
T16	432882	6352	0	0
T17	0	8537	0	0
T19	0	2010	0	0
T25	0	2	0	0
T26	0	11004	0	0
T34	0	3190	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	877121	0	0
T3	761552	6665	0	0
T5	480679	1424	0	0
T7	21642	0	0	0
T8	100170	0	0	0
T10	5232	0	0	0
T12	164418	2960	0	0
T13	319564	6381	0	0
T14	27438	0	0	0
T15	100076	0	0	0
T16	432882	6352	0	0
T17	0	8537	0	0
T19	0	2010	0	0
T25	0	2	0	0
T26	0	11004	0	0
T34	0	3190	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	877121	0	0
T3	761552	6665	0	0
T5	480679	1424	0	0
T7	21642	0	0	0
T8	100170	0	0	0
T10	5232	0	0	0
T12	164418	2960	0	0
T13	319564	6381	0	0
T14	27438	0	0	0
T15	100076	0	0	0
T16	432882	6352	0	0
T17	0	8537	0	0
T19	0	2010	0	0
T25	0	2	0	0
T26	0	11004	0	0
T34	0	3190	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	877121	0	0
T3	761552	6665	0	0
T5	480679	1424	0	0
T7	21642	0	0	0
T8	100170	0	0	0
T10	5232	0	0	0
T12	164418	2960	0	0
T13	319564	6381	0	0
T14	27438	0	0	0
T15	100076	0	0	0
T16	432882	6352	0	0
T17	0	8537	0	0
T19	0	2010	0	0
T25	0	2	0	0
T26	0	11004	0	0
T34	0	3190	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	128746256	0	0
T2	36380	36380	0	0
T3	761552	554533	0	0
T5	480679	479704	0	0
T7	21642	21642	0	0
T8	100170	0	0	0
T10	5232	5232	0	0
T12	164418	163772	0	0
T13	319564	318556	0	0
T14	27438	26910	0	0
T15	100076	99694	0	0
T16	0	397925	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156655982	877121	0	0
T3	761552	6665	0	0
T5	480679	1424	0	0
T7	21642	0	0	0
T8	100170	0	0	0
T10	5232	0	0	0
T12	164418	2960	0	0
T13	319564	6381	0	0
T14	27438	0	0	0
T15	100076	0	0	0
T16	432882	6352	0	0
T17	0	8537	0	0
T19	0	2010	0	0
T25	0	2	0	0
T26	0	11004	0	0
T34	0	3190	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	474758817	474672565	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	474758817	2351734	0	0
GntImpliesValid_A	474758817	2351734	0	0
GrantKnown_A	474758817	474672565	0	0
IdxKnown_A	474758817	474672565	0	0
IndexIsCorrect_A	474758817	2351734	0	0
LockArbDecision_A	474758817	0	0	0
NoReadyValidNoGrant_A	474758817	0	0	0
ReadyAndValidImplyGrant_A	474758817	2351734	0	0
ReqAndReadyImplyGrant_A	474758817	2351734	0	0
ReqImpliesValid_A	474758817	2351734	0	0
ReqStaysHighUntilGranted0_M	474758817	0	0	0
RoundRobin_A	474758817	9	0	956
ValidKnown_A	474758817	474672565	0	0
gen_data_port_assertion.DataFlow_A	474758817	2351734	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474758817	474672565	0	0
T1	601294	601229	0	0
T2	258278	258180	0	0
T3	799340	799270	0	0
T4	684	634	0	0
T5	148075	148066	0	0
T6	1340	1283	0	0
T7	133075	132975	0	0
T8	410689	410638	0	0
T9	1107	1007	0	0
T10	31739	31677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474758817	2351734	0	0
T1	601294	2657	0	0
T2	258278	832	0	0
T3	799340	9280	0	0
T4	684	0	0	0
T5	148075	5294	0	0
T6	1340	0	0	0
T7	133075	832	0	0
T8	410689	0	0	0
T9	1107	0	0	0
T10	31739	1088	0	0
T12	0	964	0	0
T13	0	8876	0	0
T14	0	832	0	0
T15	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474758817	2351734	0	0
T1	601294	2657	0	0
T2	258278	832	0	0
T3	799340	9280	0	0
T4	684	0	0	0
T5	148075	5294	0	0
T6	1340	0	0	0
T7	133075	832	0	0
T8	410689	0	0	0
T9	1107	0	0	0
T10	31739	1088	0	0
T12	0	964	0	0
T13	0	8876	0	0
T14	0	832	0	0
T15	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474758817	474672565	0	0
T1	601294	601229	0	0
T2	258278	258180	0	0
T3	799340	799270	0	0
T4	684	634	0	0
T5	148075	148066	0	0
T6	1340	1283	0	0
T7	133075	132975	0	0
T8	410689	410638	0	0
T9	1107	1007	0	0
T10	31739	31677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474758817	474672565	0	0
T1	601294	601229	0	0
T2	258278	258180	0	0
T3	799340	799270	0	0
T4	684	634	0	0
T5	148075	148066	0	0
T6	1340	1283	0	0
T7	133075	132975	0	0
T8	410689	410638	0	0
T9	1107	1007	0	0
T10	31739	31677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474758817	2351734	0	0
T1	601294	2657	0	0
T2	258278	832	0	0
T3	799340	9280	0	0
T4	684	0	0	0
T5	148075	5294	0	0
T6	1340	0	0	0
T7	133075	832	0	0
T8	410689	0	0	0
T9	1107	0	0	0
T10	31739	1088	0	0
T12	0	964	0	0
T13	0	8876	0	0
T14	0	832	0	0
T15	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474758817	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474758817	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474758817	2351734	0	0
T1	601294	2657	0	0
T2	258278	832	0	0
T3	799340	9280	0	0
T4	684	0	0	0
T5	148075	5294	0	0
T6	1340	0	0	0
T7	133075	832	0	0
T8	410689	0	0	0
T9	1107	0	0	0
T10	31739	1088	0	0
T12	0	964	0	0
T13	0	8876	0	0
T14	0	832	0	0
T15	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474758817	2351734	0	0
T1	601294	2657	0	0
T2	258278	832	0	0
T3	799340	9280	0	0
T4	684	0	0	0
T5	148075	5294	0	0
T6	1340	0	0	0
T7	133075	832	0	0
T8	410689	0	0	0
T9	1107	0	0	0
T10	31739	1088	0	0
T12	0	964	0	0
T13	0	8876	0	0
T14	0	832	0	0
T15	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474758817	2351734	0	0
T1	601294	2657	0	0
T2	258278	832	0	0
T3	799340	9280	0	0
T4	684	0	0	0
T5	148075	5294	0	0
T6	1340	0	0	0
T7	133075	832	0	0
T8	410689	0	0	0
T9	1107	0	0	0
T10	31739	1088	0	0
T12	0	964	0	0
T13	0	8876	0	0
T14	0	832	0	0
T15	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	474758817	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474758817	9	0	956
T24	566912	1	0	1
T30	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	888528	0	0	1
T52	7721	0	0	1
T53	2718	0	0	1
T54	183757	0	0	1
T55	181398	0	0	1
T56	13076	0	0	1
T57	4009	0	0	1
T58	1045	0	0	1
T59	523337	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474758817	474672565	0	0
T1	601294	601229	0	0
T2	258278	258180	0	0
T3	799340	799270	0	0
T4	684	634	0	0
T5	148075	148066	0	0
T6	1340	1283	0	0
T7	133075	132975	0	0
T8	410689	410638	0	0
T9	1107	1007	0	0
T10	31739	31677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474758817	2351734	0	0
T1	601294	2657	0	0
T2	258278	832	0	0
T3	799340	9280	0	0
T4	684	0	0	0
T5	148075	5294	0	0
T6	1340	0	0	0
T7	133075	832	0	0
T8	410689	0	0	0
T9	1107	0	0	0
T10	31739	1088	0	0
T12	0	964	0	0
T13	0	8876	0	0
T14	0	832	0	0
T15	0	832	0	0