Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	476785012	3760	0	0
addr_swap_data_rd_A	476785012	1656	0	0
addr_swap_mask_rd_A	476785012	1669	0	0
cfg_rd_A	476785012	2121	0	0
cmd_filter_0_rd_A	476785012	8902	0	0
cmd_filter_1_rd_A	476785012	8518	0	0
cmd_filter_2_rd_A	476785012	8537	0	0
cmd_filter_3_rd_A	476785012	8339	0	0
cmd_filter_4_rd_A	476785012	9387	0	0
cmd_filter_5_rd_A	476785012	8944	0	0
cmd_filter_6_rd_A	476785012	9665	0	0
cmd_filter_7_rd_A	476785012	7375	0	0
cmd_info_0_rd_A	476785012	4245	0	0
cmd_info_10_rd_A	476785012	4333	0	0
cmd_info_11_rd_A	476785012	4128	0	0
cmd_info_12_rd_A	476785012	4238	0	0
cmd_info_13_rd_A	476785012	4303	0	0
cmd_info_14_rd_A	476785012	4300	0	0
cmd_info_15_rd_A	476785012	4154	0	0
cmd_info_16_rd_A	476785012	4150	0	0
cmd_info_17_rd_A	476785012	4494	0	0
cmd_info_18_rd_A	476785012	4249	0	0
cmd_info_19_rd_A	476785012	4446	0	0
cmd_info_1_rd_A	476785012	4735	0	0
cmd_info_20_rd_A	476785012	4161	0	0
cmd_info_21_rd_A	476785012	4420	0	0
cmd_info_22_rd_A	476785012	4539	0	0
cmd_info_23_rd_A	476785012	4498	0	0
cmd_info_2_rd_A	476785012	4222	0	0
cmd_info_3_rd_A	476785012	4344	0	0
cmd_info_4_rd_A	476785012	4879	0	0
cmd_info_5_rd_A	476785012	4290	0	0
cmd_info_6_rd_A	476785012	4546	0	0
cmd_info_7_rd_A	476785012	4582	0	0
cmd_info_8_rd_A	476785012	4636	0	0
cmd_info_9_rd_A	476785012	4065	0	0
cmd_info_en4b_rd_A	476785012	2031	0	0
cmd_info_ex4b_rd_A	476785012	1848	0	0
cmd_info_wrdi_rd_A	476785012	1941	0	0
cmd_info_wren_rd_A	476785012	2053	0	0
intercept_en_rd_A	476785012	2470	0	0
intr_enable_rd_A	476785012	4091	0	0
jedec_cc_rd_A	476785012	1835	0	0
jedec_id_rd_A	476785012	1896	0	0
mailbox_addr_rd_A	476785012	1783	0	0
payload_swap_data_rd_A	476785012	1725	0	0
payload_swap_mask_rd_A	476785012	1602	0	0
read_threshold_rd_A	476785012	1804	0	0
tpm_access_0_rd_A	476785012	2434	0	0
tpm_access_1_rd_A	476785012	1613	0	0
tpm_cfg_rd_A	476785012	2589	0	0
tpm_did_vid_rd_A	476785012	1914	0	0
tpm_int_enable_rd_A	476785012	1791	0	0
tpm_int_status_rd_A	476785012	1678	0	0
tpm_int_vector_rd_A	476785012	1626	0	0
tpm_intf_capability_rd_A	476785012	1714	0	0
tpm_rid_rd_A	476785012	1732	0	0
tpm_sts_rd_A	476785012	1735	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	3760	0	0
T61	6059	209	0	0
T62	10431	5	0	0
T63	13856	233	0	0
T87	28382	2	0	0
T89	29048	7	0	0
T90	94237	7	0	0
T105	3804	11	0	0
T106	6305	1	0	0
T107	3780	3	0	0
T108	5235	4	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	1656	0	0
T62	10431	22	0	0
T90	94237	53	0	0
T106	6305	8	0	0
T138	20693	75	0	0
T139	13629	41	0	0
T140	8060	35	0	0
T141	13139	47	0	0
T142	7564	44	0	0
T143	9904	13	0	0
T144	13902	13	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	1669	0	0
T62	10431	17	0	0
T79	1922	4	0	0
T90	94237	71	0	0
T106	6305	4	0	0
T138	20693	75	0	0
T139	13629	9	0	0
T140	8060	18	0	0
T141	13139	31	0	0
T142	7564	8	0	0
T143	9904	16	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	2121	0	0
T62	10431	23	0	0
T79	1922	5	0	0
T90	94237	101	0	0
T106	6305	7	0	0
T138	20693	16	0	0
T139	13629	56	0	0
T140	8060	13	0	0
T141	13139	38	0	0
T142	7564	13	0	0
T143	9904	21	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	8902	0	0
T62	10431	144	0	0
T79	1922	3	0	0
T90	94237	915	0	0
T106	6305	11	0	0
T138	20693	28	0	0
T139	13629	27	0	0
T140	8060	20	0	0
T141	13139	26	0	0
T142	7564	20	0	0
T143	9904	178	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	8518	0	0
T62	10431	18	0	0
T79	1922	9	0	0
T90	94237	1147	0	0
T106	6305	12	0	0
T138	20693	52	0	0
T139	13629	36	0	0
T140	8060	28	0	0
T141	13139	44	0	0
T142	7564	7	0	0
T143	9904	23	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	8537	0	0
T62	10431	16	0	0
T79	1922	8	0	0
T90	94237	960	0	0
T106	6305	133	0	0
T138	20693	53	0	0
T139	13629	34	0	0
T140	8060	64	0	0
T141	13139	20	0	0
T142	7564	24	0	0
T143	9904	166	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	8339	0	0
T62	10431	110	0	0
T79	1922	1	0	0
T90	94237	1126	0	0
T106	6305	129	0	0
T138	20693	77	0	0
T139	13629	20	0	0
T140	8060	5	0	0
T141	13139	55	0	0
T142	7564	1	0	0
T143	9904	267	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	9387	0	0
T62	10431	261	0	0
T79	1922	5	0	0
T90	94237	948	0	0
T106	6305	140	0	0
T138	20693	83	0	0
T139	13629	70	0	0
T140	8060	12	0	0
T141	13139	27	0	0
T142	7564	12	0	0
T143	9904	18	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	8944	0	0
T62	10431	19	0	0
T79	1922	2	0	0
T90	94237	885	0	0
T106	6305	127	0	0
T138	20693	39	0	0
T139	13629	21	0	0
T140	8060	27	0	0
T141	13139	42	0	0
T142	7564	40	0	0
T143	9904	21	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	9665	0	0
T62	10431	252	0	0
T79	1922	3	0	0
T90	94237	1104	0	0
T106	6305	137	0	0
T138	20693	27	0	0
T139	13629	21	0	0
T140	8060	11	0	0
T141	13139	78	0	0
T142	7564	34	0	0
T143	9904	145	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	7375	0	0
T62	10431	122	0	0
T79	1922	5	0	0
T90	94237	838	0	0
T106	6305	134	0	0
T138	20693	93	0	0
T139	13629	57	0	0
T140	8060	16	0	0
T141	13139	64	0	0
T142	7564	1	0	0
T143	9904	13	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4245	0	0
T62	10431	62	0	0
T79	1922	7	0	0
T90	94237	295	0	0
T106	6305	53	0	0
T138	20693	73	0	0
T139	13629	26	0	0
T140	8060	36	0	0
T141	13139	41	0	0
T142	7564	3	0	0
T143	9904	81	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4333	0	0
T62	10431	48	0	0
T90	94237	502	0	0
T106	6305	4	0	0
T138	20693	58	0	0
T139	13629	24	0	0
T140	8060	48	0	0
T141	13139	94	0	0
T142	7564	18	0	0
T143	9904	84	0	0
T144	13902	40	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4128	0	0
T62	10431	7	0	0
T90	94237	485	0	0
T106	6305	60	0	0
T138	20693	88	0	0
T139	13629	3	0	0
T140	8060	33	0	0
T141	13139	46	0	0
T142	7564	48	0	0
T143	9904	16	0	0
T144	13902	30	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4238	0	0
T62	10431	91	0	0
T79	1922	3	0	0
T90	94237	405	0	0
T106	6305	4	0	0
T138	20693	66	0	0
T139	13629	43	0	0
T140	8060	9	0	0
T141	13139	47	0	0
T142	7564	23	0	0
T143	9904	76	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4303	0	0
T62	10431	70	0	0
T79	1922	5	0	0
T90	94237	334	0	0
T106	6305	12	0	0
T138	20693	52	0	0
T139	13629	33	0	0
T140	8060	21	0	0
T141	13139	26	0	0
T142	7564	10	0	0
T143	9904	122	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4300	0	0
T62	10431	50	0	0
T79	1922	5	0	0
T90	94237	489	0	0
T106	6305	51	0	0
T138	20693	53	0	0
T139	13629	23	0	0
T140	8060	49	0	0
T141	13139	31	0	0
T143	9904	45	0	0
T144	13902	34	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4154	0	0
T62	10431	21	0	0
T79	1922	3	0	0
T90	94237	363	0	0
T106	6305	35	0	0
T138	20693	60	0	0
T139	13629	69	0	0
T140	8060	43	0	0
T141	13139	11	0	0
T142	7564	14	0	0
T143	9904	75	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4150	0	0
T62	10431	62	0	0
T90	94237	303	0	0
T106	6305	55	0	0
T138	20693	80	0	0
T139	13629	67	0	0
T140	8060	23	0	0
T141	13139	28	0	0
T142	7564	39	0	0
T143	9904	16	0	0
T144	13902	38	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4494	0	0
T62	10431	60	0	0
T79	1922	1	0	0
T90	94237	373	0	0
T106	6305	67	0	0
T138	20693	37	0	0
T139	13629	53	0	0
T140	8060	25	0	0
T141	13139	17	0	0
T142	7564	28	0	0
T143	9904	67	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4249	0	0
T62	10431	137	0	0
T79	1922	9	0	0
T90	94237	342	0	0
T106	6305	8	0	0
T138	20693	76	0	0
T139	13629	55	0	0
T140	8060	17	0	0
T141	13139	65	0	0
T143	9904	61	0	0
T144	13902	32	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4446	0	0
T62	10431	43	0	0
T90	94237	373	0	0
T106	6305	49	0	0
T138	20693	31	0	0
T139	13629	44	0	0
T140	8060	39	0	0
T141	13139	32	0	0
T142	7564	20	0	0
T143	9904	101	0	0
T144	13902	68	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4735	0	0
T62	10431	130	0	0
T90	94237	438	0	0
T106	6305	4	0	0
T138	20693	115	0	0
T139	13629	82	0	0
T140	8060	23	0	0
T141	13139	60	0	0
T142	7564	29	0	0
T143	9904	35	0	0
T144	13902	28	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4161	0	0
T62	10431	79	0	0
T79	1922	7	0	0
T90	94237	410	0	0
T106	6305	6	0	0
T138	20693	58	0	0
T139	13629	9	0	0
T141	13139	32	0	0
T142	7564	44	0	0
T143	9904	103	0	0
T144	13902	51	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4420	0	0
T62	10431	108	0	0
T79	1922	4	0	0
T90	94237	355	0	0
T106	6305	5	0	0
T138	20693	84	0	0
T139	13629	34	0	0
T140	8060	40	0	0
T141	13139	26	0	0
T142	7564	6	0	0
T143	9904	66	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4539	0	0
T62	10431	123	0	0
T79	1922	3	0	0
T90	94237	411	0	0
T106	6305	5	0	0
T138	20693	116	0	0
T139	13629	77	0	0
T140	8060	9	0	0
T141	13139	38	0	0
T142	7564	9	0	0
T143	9904	113	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4498	0	0
T62	10431	71	0	0
T90	94237	514	0	0
T106	6305	6	0	0
T138	20693	84	0	0
T139	13629	50	0	0
T140	8060	6	0	0
T141	13139	68	0	0
T142	7564	10	0	0
T143	9904	53	0	0
T144	13902	57	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4222	0	0
T62	10431	82	0	0
T79	1922	2	0	0
T90	94237	456	0	0
T106	6305	2	0	0
T138	20693	29	0	0
T139	13629	42	0	0
T140	8060	42	0	0
T141	13139	36	0	0
T142	7564	22	0	0
T143	9904	96	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4344	0	0
T62	10431	18	0	0
T90	94237	392	0	0
T106	6305	52	0	0
T138	20693	75	0	0
T139	13629	62	0	0
T140	8060	32	0	0
T141	13139	37	0	0
T142	7564	41	0	0
T143	9904	66	0	0
T144	13902	26	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4879	0	0
T62	10431	16	0	0
T79	1922	5	0	0
T90	94237	470	0	0
T106	6305	28	0	0
T138	20693	48	0	0
T139	13629	39	0	0
T140	8060	28	0	0
T141	13139	55	0	0
T142	7564	31	0	0
T143	9904	61	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4290	0	0
T62	10431	55	0	0
T79	1922	7	0	0
T90	94237	486	0	0
T106	6305	40	0	0
T138	20693	34	0	0
T139	13629	14	0	0
T140	8060	33	0	0
T141	13139	29	0	0
T142	7564	30	0	0
T143	9904	116	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4546	0	0
T62	10431	48	0	0
T79	1922	5	0	0
T90	94237	560	0	0
T106	6305	44	0	0
T138	20693	70	0	0
T139	13629	28	0	0
T140	8060	7	0	0
T141	13139	36	0	0
T142	7564	16	0	0
T143	9904	62	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4582	0	0
T62	10431	18	0	0
T79	1922	3	0	0
T90	94237	393	0	0
T106	6305	49	0	0
T138	20693	60	0	0
T139	13629	56	0	0
T141	13139	50	0	0
T142	7564	24	0	0
T143	9904	77	0	0
T144	13902	30	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4636	0	0
T62	10431	108	0	0
T79	1922	8	0	0
T90	94237	601	0	0
T106	6305	14	0	0
T138	20693	67	0	0
T139	13629	56	0	0
T140	8060	24	0	0
T141	13139	8	0	0
T142	7564	31	0	0
T143	9904	19	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4065	0	0
T62	10431	10	0	0
T79	1922	5	0	0
T90	94237	306	0	0
T106	6305	3	0	0
T138	20693	88	0	0
T139	13629	65	0	0
T141	13139	51	0	0
T142	7564	2	0	0
T143	9904	52	0	0
T144	13902	21	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	2031	0	0
T62	10431	18	0	0
T79	1922	8	0	0
T90	94237	89	0	0
T106	6305	5	0	0
T138	20693	26	0	0
T139	13629	42	0	0
T140	8060	18	0	0
T141	13139	30	0	0
T142	7564	13	0	0
T143	9904	17	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	1848	0	0
T62	10431	14	0	0
T90	94237	84	0	0
T106	6305	10	0	0
T138	20693	64	0	0
T139	13629	32	0	0
T140	8060	4	0	0
T141	13139	56	0	0
T142	7564	9	0	0
T143	9904	15	0	0
T144	13902	31	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	1941	0	0
T62	10431	20	0	0
T79	1922	2	0	0
T90	94237	101	0	0
T106	6305	5	0	0
T138	20693	72	0	0
T139	13629	32	0	0
T140	8060	25	0	0
T141	13139	38	0	0
T142	7564	42	0	0
T143	9904	31	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	2053	0	0
T62	10431	19	0	0
T90	94237	114	0	0
T106	6305	8	0	0
T138	20693	55	0	0
T139	13629	22	0	0
T141	13139	56	0	0
T142	7564	10	0	0
T143	9904	23	0	0
T144	13902	73	0	0
T145	3293	8	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	2470	0	0
T62	10431	19	0	0
T79	1922	3	0	0
T90	94237	168	0	0
T106	6305	5	0	0
T138	20693	67	0	0
T139	13629	41	0	0
T140	8060	3	0	0
T141	13139	90	0	0
T142	7564	6	0	0
T143	9904	37	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	4091	0	0
T18	4446	13	0	0
T19	561840	17	0	0
T28	884088	0	0	0
T29	6608	0	0	0
T32	12346	0	0	0
T33	21010	0	0	0
T34	135623	0	0	0
T42	115751	0	0	0
T125	16777	0	0	0
T126	539426	0	0	0
T146	0	40	0	0
T147	0	63	0	0
T148	0	17	0	0
T149	0	14	0	0
T150	0	35	0	0
T151	0	27	0	0
T152	0	16	0	0
T153	0	32	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	1835	0	0
T62	10431	24	0	0
T79	1922	1	0	0
T90	94237	80	0	0
T106	6305	1	0	0
T138	20693	50	0	0
T139	13629	22	0	0
T140	8060	9	0	0
T141	13139	46	0	0
T142	7564	4	0	0
T143	9904	23	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	1896	0	0
T62	10431	25	0	0
T79	1922	5	0	0
T90	94237	86	0	0
T106	6305	8	0	0
T138	20693	71	0	0
T139	13629	36	0	0
T140	8060	41	0	0
T141	13139	18	0	0
T142	7564	40	0	0
T143	9904	30	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	1783	0	0
T62	10431	9	0	0
T79	1922	3	0	0
T90	94237	81	0	0
T106	6305	6	0	0
T138	20693	77	0	0
T139	13629	41	0	0
T140	8060	61	0	0
T141	13139	33	0	0
T142	7564	25	0	0
T143	9904	12	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	1725	0	0
T62	10431	16	0	0
T90	94237	75	0	0
T106	6305	7	0	0
T138	20693	37	0	0
T139	13629	43	0	0
T140	8060	48	0	0
T141	13139	72	0	0
T142	7564	7	0	0
T143	9904	21	0	0
T144	13902	19	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	1602	0	0
T62	10431	17	0	0
T79	1922	7	0	0
T90	94237	63	0	0
T106	6305	3	0	0
T138	20693	67	0	0
T139	13629	45	0	0
T140	8060	20	0	0
T141	13139	38	0	0
T142	7564	6	0	0
T143	9904	8	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	1804	0	0
T62	10431	10	0	0
T90	94237	46	0	0
T138	20693	105	0	0
T139	13629	57	0	0
T140	8060	30	0	0
T141	13139	50	0	0
T142	7564	12	0	0
T143	9904	14	0	0
T144	13902	21	0	0
T154	8434	8	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	2434	0	0
T62	10431	21	0	0
T79	1922	2	0	0
T90	94237	206	0	0
T106	6305	21	0	0
T138	20693	68	0	0
T139	13629	46	0	0
T140	8060	22	0	0
T141	13139	44	0	0
T142	7564	28	0	0
T143	9904	40	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	1613	0	0
T62	10431	5	0	0
T79	1922	6	0	0
T90	94237	59	0	0
T106	6305	12	0	0
T138	20693	63	0	0
T139	13629	31	0	0
T140	8060	14	0	0
T141	13139	57	0	0
T142	7564	9	0	0
T143	9904	8	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	2589	0	0
T62	10431	20	0	0
T79	1922	5	0	0
T90	94237	214	0	0
T106	6305	26	0	0
T138	20693	67	0	0
T139	13629	18	0	0
T140	8060	1	0	0
T141	13139	31	0	0
T142	7564	39	0	0
T143	9904	26	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	1914	0	0
T62	10431	17	0	0
T79	1922	5	0	0
T90	94237	97	0	0
T106	6305	11	0	0
T138	20693	32	0	0
T139	13629	24	0	0
T140	8060	18	0	0
T141	13139	37	0	0
T142	7564	28	0	0
T143	9904	18	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	1791	0	0
T62	10431	22	0	0
T63	13856	3	0	0
T79	1922	3	0	0
T90	94237	62	0	0
T106	6305	8	0	0
T138	20693	53	0	0
T139	13629	47	0	0
T140	8060	21	0	0
T141	13139	34	0	0
T142	7564	29	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	1678	0	0
T62	10431	12	0	0
T79	1922	4	0	0
T90	94237	78	0	0
T106	6305	2	0	0
T138	20693	72	0	0
T139	13629	54	0	0
T141	13139	48	0	0
T142	7564	11	0	0
T143	9904	16	0	0
T144	13902	17	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	1626	0	0
T62	10431	13	0	0
T79	1922	5	0	0
T90	94237	49	0	0
T106	6305	8	0	0
T138	20693	35	0	0
T139	13629	48	0	0
T140	8060	4	0	0
T141	13139	51	0	0
T142	7564	28	0	0
T143	9904	9	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	1714	0	0
T62	10431	13	0	0
T79	1922	6	0	0
T90	94237	66	0	0
T106	6305	10	0	0
T138	20693	50	0	0
T139	13629	47	0	0
T140	8060	56	0	0
T141	13139	64	0	0
T142	7564	10	0	0
T143	9904	17	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	1732	0	0
T62	10431	16	0	0
T90	94237	65	0	0
T106	6305	6	0	0
T138	20693	74	0	0
T139	13629	31	0	0
T140	8060	16	0	0
T141	13139	31	0	0
T142	7564	15	0	0
T143	9904	7	0	0
T144	13902	47	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476785012	1735	0	0
T62	10431	15	0	0
T63	13856	9	0	0
T79	1922	8	0	0
T90	94237	62	0	0
T106	6305	14	0	0
T138	20693	53	0	0
T139	13629	53	0	0
T140	8060	20	0	0
T141	13139	36	0	0
T142	7564	30	0	0