Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3741512	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4268818

1

T1

1548

T2

1283

T3

992

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4383250	1			T1	1357		T2	793		T3	199
values[0x0]	1812057	1			T1	439		T2	406		T3	436
values[0x1]	1815023	1			T1	452		T2	477		T3	455

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2643105	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5367225

1

T1

1666

T2

1367

T3

1003

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	34152	1			T4	8		T8	1		T9	1
valid_sources[0x01]	28456	1			T4	4		T8	5		T10	50
valid_sources[0x02]	29544	1			T4	2		T8	3		T10	48
valid_sources[0x03]	29831	1			T4	3		T8	5		T10	62
valid_sources[0x04]	30440	1			T4	1		T8	3		T9	3
valid_sources[0x05]	28410	1			T4	3		T8	3		T10	41
valid_sources[0x06]	31580	1			T4	5		T8	5		T10	48
valid_sources[0x07]	31652	1			T4	4		T8	3		T9	2
valid_sources[0x08]	29824	1			T4	10		T8	1		T10	110
valid_sources[0x09]	37254	1			T4	5		T8	13		T10	42
valid_sources[0x0a]	28255	1			T4	8		T8	6		T10	56
valid_sources[0x0b]	28675	1			T4	5		T8	6		T9	1
valid_sources[0x0c]	29785	1			T4	7		T8	8		T9	1
valid_sources[0x0d]	27691	1			T4	6		T8	5		T9	1
valid_sources[0x0e]	29091	1			T4	8		T8	11		T10	51
valid_sources[0x0f]	31103	1			T4	3		T8	1		T10	52
valid_sources[0x10]	27677	1			T4	3		T8	4		T10	89
valid_sources[0x11]	27308	1			T4	8		T8	15		T10	52
valid_sources[0x12]	30816	1			T4	2		T8	6		T10	58
valid_sources[0x13]	29904	1			T8	5		T10	61		T11	1
valid_sources[0x14]	37742	1			T4	5		T8	7		T9	2
valid_sources[0x15]	31448	1			T4	4		T6	416		T8	8
valid_sources[0x16]	36059	1			T4	2		T8	2		T10	34
valid_sources[0x17]	69499	1			T8	3		T9	2		T10	64
valid_sources[0x18]	27969	1			T4	8		T8	6		T9	146
valid_sources[0x19]	29551	1			T4	7		T8	4		T10	75
valid_sources[0x1a]	31390	1			T4	7		T8	3		T10	63
valid_sources[0x1b]	29054	1			T4	3		T8	2		T10	41
valid_sources[0x1c]	29913	1			T4	4		T8	4		T10	54
valid_sources[0x1d]	28351	1			T8	3		T9	2		T10	52
valid_sources[0x1e]	28250	1			T4	1		T8	2		T10	40
valid_sources[0x1f]	29715	1			T4	13		T8	1		T10	44
valid_sources[0x20]	29708	1			T4	8		T8	2		T10	54
valid_sources[0x21]	31839	1			T4	3		T8	3		T10	72
valid_sources[0x22]	30211	1			T4	6		T8	9		T10	56
valid_sources[0x23]	27731	1			T4	7		T8	7		T10	54
valid_sources[0x24]	28443	1			T4	7		T8	4		T10	34
valid_sources[0x25]	28820	1			T4	6		T8	4		T10	55
valid_sources[0x26]	33115	1			T4	7		T8	7		T9	1
valid_sources[0x27]	29627	1			T4	3		T8	5		T10	53
valid_sources[0x28]	27769	1			T4	5		T8	3		T10	59
valid_sources[0x29]	29413	1			T4	10		T8	5		T9	1
valid_sources[0x2a]	29290	1			T4	3		T8	4		T9	1
valid_sources[0x2b]	29894	1			T4	5		T10	35		T11	2
valid_sources[0x2c]	30652	1			T4	5		T8	7		T10	51
valid_sources[0x2d]	31495	1			T4	11		T10	61		T12	1
valid_sources[0x2e]	32210	1			T4	10		T8	10		T9	1
valid_sources[0x2f]	28715	1			T4	3		T8	3		T10	44
valid_sources[0x30]	31632	1			T4	8		T8	6		T10	76
valid_sources[0x31]	31676	1			T4	7		T8	4		T9	1
valid_sources[0x32]	29777	1			T4	2		T8	1		T9	2
valid_sources[0x33]	31873	1			T4	5		T8	4		T10	65
valid_sources[0x34]	29171	1			T4	5		T8	3		T10	81
valid_sources[0x35]	29205	1			T4	4		T8	6		T9	139
valid_sources[0x36]	32746	1			T1	1795		T4	10		T8	6
valid_sources[0x37]	28565	1			T4	8		T8	1		T9	1
valid_sources[0x38]	31744	1			T4	3		T8	6		T9	1
valid_sources[0x39]	29018	1			T4	2		T8	4		T10	72
valid_sources[0x3a]	30755	1			T4	2		T10	49		T12	11
valid_sources[0x3b]	30376	1			T4	10		T8	5		T9	3
valid_sources[0x3c]	28421	1			T4	3		T8	4		T10	49
valid_sources[0x3d]	31047	1			T4	3		T8	1		T9	418
valid_sources[0x3e]	30063	1			T8	5		T10	88		T12	5
valid_sources[0x3f]	29441	1			T4	2		T8	8		T10	48
valid_sources[0x40]	33721	1			T4	7		T8	4		T10	46
valid_sources[0x41]	28794	1			T4	4		T8	6		T9	1
valid_sources[0x42]	33444	1			T4	5		T8	5		T9	2
valid_sources[0x43]	30639	1			T4	1		T8	4		T10	62
valid_sources[0x44]	28688	1			T4	3		T8	2		T10	54
valid_sources[0x45]	35071	1			T4	4		T8	10		T10	23
valid_sources[0x46]	27378	1			T4	3		T8	5		T10	92
valid_sources[0x47]	31240	1			T4	1		T8	6		T9	1
valid_sources[0x48]	30641	1			T4	5		T8	4		T9	858
valid_sources[0x49]	29514	1			T4	1		T8	3		T10	48
valid_sources[0x4a]	31650	1			T4	4		T8	4		T9	111
valid_sources[0x4b]	40112	1			T4	1		T8	1		T10	25
valid_sources[0x4c]	32976	1			T8	3		T10	56		T12	7
valid_sources[0x4d]	31323	1			T4	3		T8	5		T10	65
valid_sources[0x4e]	30591	1			T4	6		T8	2		T9	1
valid_sources[0x4f]	28703	1			T4	1		T10	57		T12	6
valid_sources[0x50]	31188	1			T4	7		T8	1		T10	50
valid_sources[0x51]	29565	1			T2	798		T4	5		T8	3
valid_sources[0x52]	29210	1			T4	7		T8	7		T10	64
valid_sources[0x53]	31965	1			T4	8		T8	11		T10	50
valid_sources[0x54]	27067	1			T4	6		T8	5		T10	49
valid_sources[0x55]	27773	1			T4	5		T8	1		T10	35
valid_sources[0x56]	31894	1			T4	9		T8	5		T10	65
valid_sources[0x57]	30599	1			T4	1		T8	3		T9	1
valid_sources[0x58]	27896	1			T4	8		T8	2		T10	41
valid_sources[0x59]	34554	1			T4	8		T8	2		T10	67
valid_sources[0x5a]	29969	1			T8	3		T10	43		T12	1
valid_sources[0x5b]	29975	1			T4	4		T8	4		T10	46
valid_sources[0x5c]	30335	1			T4	1		T8	1		T9	1
valid_sources[0x5d]	28978	1			T4	10		T8	5		T9	1
valid_sources[0x5e]	36297	1			T4	10		T8	4		T10	65
valid_sources[0x5f]	29553	1			T4	3		T8	2		T10	67
valid_sources[0x60]	31660	1			T4	7		T8	4		T10	52
valid_sources[0x61]	30078	1			T4	6		T8	2		T10	47
valid_sources[0x62]	31303	1			T4	4		T8	1		T10	70
valid_sources[0x63]	28708	1			T4	5		T8	8		T9	1
valid_sources[0x64]	30542	1			T4	3		T8	1		T9	1
valid_sources[0x65]	29770	1			T4	16		T8	5		T10	44
valid_sources[0x66]	33438	1			T1	1		T4	4		T8	7
valid_sources[0x67]	28345	1			T4	8		T8	2		T10	34
valid_sources[0x68]	28838	1			T4	7		T10	76		T13	5
valid_sources[0x69]	47392	1			T4	4		T8	6		T9	1
valid_sources[0x6a]	33028	1			T4	6		T8	1		T10	65
valid_sources[0x6b]	38220	1			T4	6		T8	1		T10	70
valid_sources[0x6c]	29551	1			T4	3		T8	8		T10	78
valid_sources[0x6d]	30430	1			T4	6		T8	2		T10	69
valid_sources[0x6e]	30358	1			T4	13		T8	3		T10	94
valid_sources[0x6f]	33140	1			T4	3		T8	5		T9	1
valid_sources[0x70]	31097	1			T4	4		T8	2		T10	77
valid_sources[0x71]	36032	1			T4	2		T8	9		T10	66
valid_sources[0x72]	30330	1			T4	5		T8	3		T10	42
valid_sources[0x73]	30861	1			T1	452		T4	4		T8	1
valid_sources[0x74]	29988	1			T4	10		T6	462		T8	2
valid_sources[0x75]	30422	1			T4	3		T8	7		T10	28
valid_sources[0x76]	29385	1			T4	6		T8	7		T10	70
valid_sources[0x77]	33687	1			T4	8		T8	7		T9	97
valid_sources[0x78]	28362	1			T4	11		T8	7		T10	56
valid_sources[0x79]	29457	1			T4	3		T8	2		T10	60
valid_sources[0x7a]	34698	1			T4	3		T8	15		T10	37
valid_sources[0x7b]	39515	1			T4	5		T8	2		T10	33
valid_sources[0x7c]	29078	1			T4	3		T8	4		T10	54
valid_sources[0x7d]	29920	1			T4	3		T8	5		T10	44
valid_sources[0x7e]	33559	1			T4	6		T9	624		T10	42
valid_sources[0x7f]	31464	1			T4	4		T8	10		T10	40
valid_sources[0x80]	30826	1			T4	9		T8	9		T10	51

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

992740

1

T1

671

T2

404

T3

109

values[0x0]

all_enables

biggest_size

1649629

1

T1

435

T2

406

T3

434

values[0x1]

all_enables

biggest_size

1626449

1

T1

442

T2

473

T3

449