Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3763512

1

T1

700

T2

393

T3

98

full_word

4270126

1

T1

1548

T2

1283

T3

992

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8033218	1			T1	2248		T2	1676		T3	1090
auto[TlIntgErrCmd]	129	1			T77	8		T106	4		T107	5
auto[TlIntgErrData]	127	1			T77	5		T106	1		T107	6
auto[TlIntgErrBoth]	164	1			T77	7		T106	5		T107	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4386719

1

T1

1357

T2

793

T3

199

auto[1]

3646919

1

T1

891

T2

883

T3

891

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3393481	1			T1	686		T2	389		T3	90
auto[TlIntgErrNone]	partial	auto[1]	369648	1			T1	14		T2	4		T3	8
auto[TlIntgErrNone]	full_word	auto[0]	993030	1			T1	671		T2	404		T3	109
auto[TlIntgErrNone]	full_word	auto[1]	3277059	1			T1	877		T2	879		T3	883
auto[TlIntgErrCmd]	partial	auto[0]	58	1			T77	3		T106	2		T107	2
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T77	5		T106	2		T107	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T175	1		T158	1		T176	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T107	1		T118	2		T174	1
auto[TlIntgErrData]	partial	auto[0]	72	1			T77	1		T107	3		T118	3
auto[TlIntgErrData]	partial	auto[1]	46	1			T77	3		T106	1		T107	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T77	1		T177	3		T178	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T107	1		T179	1		T173	1
auto[TlIntgErrBoth]	partial	auto[0]	61	1			T106	1		T107	4		T118	2
auto[TlIntgErrBoth]	partial	auto[1]	86	1			T77	5		T106	4		T107	4
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T77	2		T118	1		T156	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T107	1		T118	1		T172	1