Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T33,T35
1	0	Covered	T8,T33,T35

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T30
1	0	Unreachable
1	1	Covered	T8,T33,T35

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T10,T33

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T33
1	0	Covered	T9,T10,T33

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T9,T10,T33

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T9,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	770264730	616511433	0	0
CheckNGreaterZero_A	2862	2862	0	0
GntImpliesReady_A	770264730	3713063	0	0
GntImpliesValid_A	770264730	3713063	0	0
GrantKnown_A	770264730	616511433	0	0
IdxKnown_A	770264730	616511433	0	0
IndexIsCorrect_A	770264730	3713063	0	0
LockArbDecision_A	770264730	0	0	0
NoReadyValidNoGrant_A	770264730	0	0	0
ReadyAndValidImplyGrant_A	770264730	3713063	0	0
ReqAndReadyImplyGrant_A	770264730	3713063	0	0
ReqImpliesValid_A	770264730	3713063	0	0
ReqStaysHighUntilGranted0_M	770264730	0	0	0
RoundRobin_A	770264730	8	0	954
ValidKnown_A	770264730	616511433	0	0
gen_data_port_assertion.DataFlow_A	770264730	3713063	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770264730	616511433	0	0
T1	42535	42478	0	0
T2	28227	28066	0	0
T3	31503	30919	0	0
T4	19501	19446	0	0
T5	7549	7450	0	0
T6	139966	139677	0	0
T7	819	762	0	0
T8	19129	16804	0	0
T9	940697	655058	0	0
T10	694315	566993	0	0
T11	82268	39672	0	0
T12	11454	11454	0	0
T13	41548	41296	0	0
T14	0	221912	0	0
T23	0	69248	0	0
T25	0	5800	0	0
T30	432	432	0	0
T33	0	239696	0	0
T34	0	648	0	0
T35	0	136	0	0
T36	0	136624	0	0
T44	136992	0	0	0
T50	9416	0	0	0
T55	8713	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2862	2862	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770264730	3713063	0	0
T1	32779	832	0	0
T2	19828	832	0	0
T3	19001	832	0	0
T4	11037	832	0	0
T5	7533	832	0	0
T6	50788	832	0	0
T7	819	0	0	0
T8	17032	194	0	0
T9	940697	7258	0	0
T10	694315	20070	0	0
T11	82268	0	0	0
T12	22908	832	0	0
T13	83096	0	0	0
T14	0	13823	0	0
T23	0	3380	0	0
T25	0	282	0	0
T26	0	19	0	0
T30	864	0	0	0
T33	290125	3076	0	0
T35	0	3	0	0
T36	0	7835	0	0
T39	0	10343	0	0
T43	0	2676	0	0
T44	273984	0	0	0
T50	18832	0	0	0
T51	0	5402	0	0
T55	17426	0	0	0
T56	0	4748	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770264730	3713063	0	0
T1	32779	832	0	0
T2	19828	832	0	0
T3	19001	832	0	0
T4	11037	832	0	0
T5	7533	832	0	0
T6	50788	832	0	0
T7	819	0	0	0
T8	17032	194	0	0
T9	940697	7258	0	0
T10	694315	20070	0	0
T11	82268	0	0	0
T12	22908	832	0	0
T13	83096	0	0	0
T14	0	13823	0	0
T23	0	3380	0	0
T25	0	282	0	0
T26	0	19	0	0
T30	864	0	0	0
T33	290125	3076	0	0
T35	0	3	0	0
T36	0	7835	0	0
T39	0	10343	0	0
T43	0	2676	0	0
T44	273984	0	0	0
T50	18832	0	0	0
T51	0	5402	0	0
T55	17426	0	0	0
T56	0	4748	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770264730	616511433	0	0
T1	42535	42478	0	0
T2	28227	28066	0	0
T3	31503	30919	0	0
T4	19501	19446	0	0
T5	7549	7450	0	0
T6	139966	139677	0	0
T7	819	762	0	0
T8	19129	16804	0	0
T9	940697	655058	0	0
T10	694315	566993	0	0
T11	82268	39672	0	0
T12	11454	11454	0	0
T13	41548	41296	0	0
T14	0	221912	0	0
T23	0	69248	0	0
T25	0	5800	0	0
T30	432	432	0	0
T33	0	239696	0	0
T34	0	648	0	0
T35	0	136	0	0
T36	0	136624	0	0
T44	136992	0	0	0
T50	9416	0	0	0
T55	8713	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770264730	616511433	0	0
T1	42535	42478	0	0
T2	28227	28066	0	0
T3	31503	30919	0	0
T4	19501	19446	0	0
T5	7549	7450	0	0
T6	139966	139677	0	0
T7	819	762	0	0
T8	19129	16804	0	0
T9	940697	655058	0	0
T10	694315	566993	0	0
T11	82268	39672	0	0
T12	11454	11454	0	0
T13	41548	41296	0	0
T14	0	221912	0	0
T23	0	69248	0	0
T25	0	5800	0	0
T30	432	432	0	0
T33	0	239696	0	0
T34	0	648	0	0
T35	0	136	0	0
T36	0	136624	0	0
T44	136992	0	0	0
T50	9416	0	0	0
T55	8713	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770264730	3713063	0	0
T1	32779	832	0	0
T2	19828	832	0	0
T3	19001	832	0	0
T4	11037	832	0	0
T5	7533	832	0	0
T6	50788	832	0	0
T7	819	0	0	0
T8	17032	194	0	0
T9	940697	7258	0	0
T10	694315	20070	0	0
T11	82268	0	0	0
T12	22908	832	0	0
T13	83096	0	0	0
T14	0	13823	0	0
T23	0	3380	0	0
T25	0	282	0	0
T26	0	19	0	0
T30	864	0	0	0
T33	290125	3076	0	0
T35	0	3	0	0
T36	0	7835	0	0
T39	0	10343	0	0
T43	0	2676	0	0
T44	273984	0	0	0
T50	18832	0	0	0
T51	0	5402	0	0
T55	17426	0	0	0
T56	0	4748	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770264730	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770264730	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770264730	3713063	0	0
T1	32779	832	0	0
T2	19828	832	0	0
T3	19001	832	0	0
T4	11037	832	0	0
T5	7533	832	0	0
T6	50788	832	0	0
T7	819	0	0	0
T8	17032	194	0	0
T9	940697	7258	0	0
T10	694315	20070	0	0
T11	82268	0	0	0
T12	22908	832	0	0
T13	83096	0	0	0
T14	0	13823	0	0
T23	0	3380	0	0
T25	0	282	0	0
T26	0	19	0	0
T30	864	0	0	0
T33	290125	3076	0	0
T35	0	3	0	0
T36	0	7835	0	0
T39	0	10343	0	0
T43	0	2676	0	0
T44	273984	0	0	0
T50	18832	0	0	0
T51	0	5402	0	0
T55	17426	0	0	0
T56	0	4748	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770264730	3713063	0	0
T1	32779	832	0	0
T2	19828	832	0	0
T3	19001	832	0	0
T4	11037	832	0	0
T5	7533	832	0	0
T6	50788	832	0	0
T7	819	0	0	0
T8	17032	194	0	0
T9	940697	7258	0	0
T10	694315	20070	0	0
T11	82268	0	0	0
T12	22908	832	0	0
T13	83096	0	0	0
T14	0	13823	0	0
T23	0	3380	0	0
T25	0	282	0	0
T26	0	19	0	0
T30	864	0	0	0
T33	290125	3076	0	0
T35	0	3	0	0
T36	0	7835	0	0
T39	0	10343	0	0
T43	0	2676	0	0
T44	273984	0	0	0
T50	18832	0	0	0
T51	0	5402	0	0
T55	17426	0	0	0
T56	0	4748	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770264730	3713063	0	0
T1	32779	832	0	0
T2	19828	832	0	0
T3	19001	832	0	0
T4	11037	832	0	0
T5	7533	832	0	0
T6	50788	832	0	0
T7	819	0	0	0
T8	17032	194	0	0
T9	940697	7258	0	0
T10	694315	20070	0	0
T11	82268	0	0	0
T12	22908	832	0	0
T13	83096	0	0	0
T14	0	13823	0	0
T23	0	3380	0	0
T25	0	282	0	0
T26	0	19	0	0
T30	864	0	0	0
T33	290125	3076	0	0
T35	0	3	0	0
T36	0	7835	0	0
T39	0	10343	0	0
T43	0	2676	0	0
T44	273984	0	0	0
T50	18832	0	0	0
T51	0	5402	0	0
T55	17426	0	0	0
T56	0	4748	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	770264730	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770264730	8	0	954
T15	345685	0	0	1
T49	598366	1	0	1
T52	237315	0	0	1
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	31005	0	0	1
T65	35675	0	0	1
T66	417976	0	0	1
T67	682716	0	0	1
T68	290539	0	0	1
T69	12052	0	0	1
T70	1289	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770264730	616511433	0	0
T1	42535	42478	0	0
T2	28227	28066	0	0
T3	31503	30919	0	0
T4	19501	19446	0	0
T5	7549	7450	0	0
T6	139966	139677	0	0
T7	819	762	0	0
T8	19129	16804	0	0
T9	940697	655058	0	0
T10	694315	566993	0	0
T11	82268	39672	0	0
T12	11454	11454	0	0
T13	41548	41296	0	0
T14	0	221912	0	0
T23	0	69248	0	0
T25	0	5800	0	0
T30	432	432	0	0
T33	0	239696	0	0
T34	0	648	0	0
T35	0	136	0	0
T36	0	136624	0	0
T44	136992	0	0	0
T50	9416	0	0	0
T55	8713	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770264730	3713063	0	0
T1	32779	832	0	0
T2	19828	832	0	0
T3	19001	832	0	0
T4	11037	832	0	0
T5	7533	832	0	0
T6	50788	832	0	0
T7	819	0	0	0
T8	17032	194	0	0
T9	940697	7258	0	0
T10	694315	20070	0	0
T11	82268	0	0	0
T12	22908	832	0	0
T13	83096	0	0	0
T14	0	13823	0	0
T23	0	3380	0	0
T25	0	282	0	0
T26	0	19	0	0
T30	864	0	0	0
T33	290125	3076	0	0
T35	0	3	0	0
T36	0	7835	0	0
T39	0	10343	0	0
T43	0	2676	0	0
T44	273984	0	0	0
T50	18832	0	0	0
T51	0	5402	0	0
T55	17426	0	0	0
T56	0	4748	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T33,T35
1	0	Covered	T8,T33,T35

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T30
1	0	Unreachable
1	1	Covered	T8,T33,T35

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T8,T33,T35
0	0	1	Unreachable
0	0	0	Covered	T8,T11,T30

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8,T33,T35
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8,T33,T35
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	152304104	30601396	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	152304104	651954	0	0
GntImpliesValid_A	152304104	651954	0	0
GrantKnown_A	152304104	30601396	0	0
IdxKnown_A	152304104	30601396	0	0
IndexIsCorrect_A	152304104	651954	0	0
LockArbDecision_A	152304104	0	0	0
NoReadyValidNoGrant_A	152304104	0	0	0
ReadyAndValidImplyGrant_A	152304104	651954	0	0
ReqAndReadyImplyGrant_A	152304104	651954	0	0
ReqImpliesValid_A	152304104	651954	0	0
ReqStaysHighUntilGranted0_M	152304104	0	0	0
RoundRobin_A	152304104	0	0	0
ValidKnown_A	152304104	30601396	0	0
gen_data_port_assertion.DataFlow_A	152304104	651954	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	30601396	0	0
T8	2097	1944	0	0
T9	282677	0	0	0
T10	126796	0	0	0
T11	41134	39672	0	0
T12	11454	0	0	0
T13	41548	0	0	0
T14	0	221912	0	0
T23	0	69248	0	0
T25	0	5800	0	0
T30	432	432	0	0
T33	0	239696	0	0
T34	0	648	0	0
T35	0	136	0	0
T36	0	136624	0	0
T44	136992	0	0	0
T50	9416	0	0	0
T55	8713	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	651954	0	0
T8	2097	145	0	0
T9	282677	0	0	0
T10	126796	0	0	0
T11	41134	0	0	0
T12	11454	0	0	0
T13	41548	0	0	0
T14	0	3548	0	0
T23	0	2987	0	0
T25	0	147	0	0
T30	432	0	0	0
T33	0	2553	0	0
T35	0	3	0	0
T36	0	5715	0	0
T39	0	5112	0	0
T44	136992	0	0	0
T50	9416	0	0	0
T51	0	5402	0	0
T55	8713	0	0	0
T56	0	4748	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	651954	0	0
T8	2097	145	0	0
T9	282677	0	0	0
T10	126796	0	0	0
T11	41134	0	0	0
T12	11454	0	0	0
T13	41548	0	0	0
T14	0	3548	0	0
T23	0	2987	0	0
T25	0	147	0	0
T30	432	0	0	0
T33	0	2553	0	0
T35	0	3	0	0
T36	0	5715	0	0
T39	0	5112	0	0
T44	136992	0	0	0
T50	9416	0	0	0
T51	0	5402	0	0
T55	8713	0	0	0
T56	0	4748	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	30601396	0	0
T8	2097	1944	0	0
T9	282677	0	0	0
T10	126796	0	0	0
T11	41134	39672	0	0
T12	11454	0	0	0
T13	41548	0	0	0
T14	0	221912	0	0
T23	0	69248	0	0
T25	0	5800	0	0
T30	432	432	0	0
T33	0	239696	0	0
T34	0	648	0	0
T35	0	136	0	0
T36	0	136624	0	0
T44	136992	0	0	0
T50	9416	0	0	0
T55	8713	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	30601396	0	0
T8	2097	1944	0	0
T9	282677	0	0	0
T10	126796	0	0	0
T11	41134	39672	0	0
T12	11454	0	0	0
T13	41548	0	0	0
T14	0	221912	0	0
T23	0	69248	0	0
T25	0	5800	0	0
T30	432	432	0	0
T33	0	239696	0	0
T34	0	648	0	0
T35	0	136	0	0
T36	0	136624	0	0
T44	136992	0	0	0
T50	9416	0	0	0
T55	8713	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	651954	0	0
T8	2097	145	0	0
T9	282677	0	0	0
T10	126796	0	0	0
T11	41134	0	0	0
T12	11454	0	0	0
T13	41548	0	0	0
T14	0	3548	0	0
T23	0	2987	0	0
T25	0	147	0	0
T30	432	0	0	0
T33	0	2553	0	0
T35	0	3	0	0
T36	0	5715	0	0
T39	0	5112	0	0
T44	136992	0	0	0
T50	9416	0	0	0
T51	0	5402	0	0
T55	8713	0	0	0
T56	0	4748	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	651954	0	0
T8	2097	145	0	0
T9	282677	0	0	0
T10	126796	0	0	0
T11	41134	0	0	0
T12	11454	0	0	0
T13	41548	0	0	0
T14	0	3548	0	0
T23	0	2987	0	0
T25	0	147	0	0
T30	432	0	0	0
T33	0	2553	0	0
T35	0	3	0	0
T36	0	5715	0	0
T39	0	5112	0	0
T44	136992	0	0	0
T50	9416	0	0	0
T51	0	5402	0	0
T55	8713	0	0	0
T56	0	4748	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	651954	0	0
T8	2097	145	0	0
T9	282677	0	0	0
T10	126796	0	0	0
T11	41134	0	0	0
T12	11454	0	0	0
T13	41548	0	0	0
T14	0	3548	0	0
T23	0	2987	0	0
T25	0	147	0	0
T30	432	0	0	0
T33	0	2553	0	0
T35	0	3	0	0
T36	0	5715	0	0
T39	0	5112	0	0
T44	136992	0	0	0
T50	9416	0	0	0
T51	0	5402	0	0
T55	8713	0	0	0
T56	0	4748	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	651954	0	0
T8	2097	145	0	0
T9	282677	0	0	0
T10	126796	0	0	0
T11	41134	0	0	0
T12	11454	0	0	0
T13	41548	0	0	0
T14	0	3548	0	0
T23	0	2987	0	0
T25	0	147	0	0
T30	432	0	0	0
T33	0	2553	0	0
T35	0	3	0	0
T36	0	5715	0	0
T39	0	5112	0	0
T44	136992	0	0	0
T50	9416	0	0	0
T51	0	5402	0	0
T55	8713	0	0	0
T56	0	4748	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	30601396	0	0
T8	2097	1944	0	0
T9	282677	0	0	0
T10	126796	0	0	0
T11	41134	39672	0	0
T12	11454	0	0	0
T13	41548	0	0	0
T14	0	221912	0	0
T23	0	69248	0	0
T25	0	5800	0	0
T30	432	432	0	0
T33	0	239696	0	0
T34	0	648	0	0
T35	0	136	0	0
T36	0	136624	0	0
T44	136992	0	0	0
T50	9416	0	0	0
T55	8713	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	651954	0	0
T8	2097	145	0	0
T9	282677	0	0	0
T10	126796	0	0	0
T11	41134	0	0	0
T12	11454	0	0	0
T13	41548	0	0	0
T14	0	3548	0	0
T23	0	2987	0	0
T25	0	147	0	0
T30	432	0	0	0
T33	0	2553	0	0
T35	0	3	0	0
T36	0	5715	0	0
T39	0	5112	0	0
T44	136992	0	0	0
T50	9416	0	0	0
T51	0	5402	0	0
T55	8713	0	0	0
T56	0	4748	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T10,T33

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T33
1	0	Covered	T9,T10,T33

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T9,T10,T33

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T33
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T9,T10,T33
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T33
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T33
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	152304104	120337255	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	152304104	792770	0	0
GntImpliesValid_A	152304104	792770	0	0
GrantKnown_A	152304104	120337255	0	0
IdxKnown_A	152304104	120337255	0	0
IndexIsCorrect_A	152304104	792770	0	0
LockArbDecision_A	152304104	0	0	0
NoReadyValidNoGrant_A	152304104	0	0	0
ReadyAndValidImplyGrant_A	152304104	792770	0	0
ReqAndReadyImplyGrant_A	152304104	792770	0	0
ReqImpliesValid_A	152304104	792770	0	0
ReqStaysHighUntilGranted0_M	152304104	0	0	0
RoundRobin_A	152304104	0	0	0
ValidKnown_A	152304104	120337255	0	0
gen_data_port_assertion.DataFlow_A	152304104	792770	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	120337255	0	0
T1	9756	9756	0	0
T2	8399	8304	0	0
T3	12502	12014	0	0
T4	8464	8464	0	0
T5	16	16	0	0
T6	89178	88954	0	0
T8	2097	0	0	0
T9	282677	279804	0	0
T10	126796	126346	0	0
T11	41134	0	0	0
T12	0	11454	0	0
T13	0	41296	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	792770	0	0
T9	282677	1189	0	0
T10	126796	8026	0	0
T11	41134	0	0	0
T12	11454	0	0	0
T13	41548	0	0	0
T14	0	10275	0	0
T23	0	393	0	0
T25	0	135	0	0
T26	0	19	0	0
T30	432	0	0	0
T33	290125	523	0	0
T36	0	2120	0	0
T39	0	5231	0	0
T43	0	2676	0	0
T44	136992	0	0	0
T50	9416	0	0	0
T55	8713	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	792770	0	0
T9	282677	1189	0	0
T10	126796	8026	0	0
T11	41134	0	0	0
T12	11454	0	0	0
T13	41548	0	0	0
T14	0	10275	0	0
T23	0	393	0	0
T25	0	135	0	0
T26	0	19	0	0
T30	432	0	0	0
T33	290125	523	0	0
T36	0	2120	0	0
T39	0	5231	0	0
T43	0	2676	0	0
T44	136992	0	0	0
T50	9416	0	0	0
T55	8713	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	120337255	0	0
T1	9756	9756	0	0
T2	8399	8304	0	0
T3	12502	12014	0	0
T4	8464	8464	0	0
T5	16	16	0	0
T6	89178	88954	0	0
T8	2097	0	0	0
T9	282677	279804	0	0
T10	126796	126346	0	0
T11	41134	0	0	0
T12	0	11454	0	0
T13	0	41296	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	120337255	0	0
T1	9756	9756	0	0
T2	8399	8304	0	0
T3	12502	12014	0	0
T4	8464	8464	0	0
T5	16	16	0	0
T6	89178	88954	0	0
T8	2097	0	0	0
T9	282677	279804	0	0
T10	126796	126346	0	0
T11	41134	0	0	0
T12	0	11454	0	0
T13	0	41296	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	792770	0	0
T9	282677	1189	0	0
T10	126796	8026	0	0
T11	41134	0	0	0
T12	11454	0	0	0
T13	41548	0	0	0
T14	0	10275	0	0
T23	0	393	0	0
T25	0	135	0	0
T26	0	19	0	0
T30	432	0	0	0
T33	290125	523	0	0
T36	0	2120	0	0
T39	0	5231	0	0
T43	0	2676	0	0
T44	136992	0	0	0
T50	9416	0	0	0
T55	8713	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	792770	0	0
T9	282677	1189	0	0
T10	126796	8026	0	0
T11	41134	0	0	0
T12	11454	0	0	0
T13	41548	0	0	0
T14	0	10275	0	0
T23	0	393	0	0
T25	0	135	0	0
T26	0	19	0	0
T30	432	0	0	0
T33	290125	523	0	0
T36	0	2120	0	0
T39	0	5231	0	0
T43	0	2676	0	0
T44	136992	0	0	0
T50	9416	0	0	0
T55	8713	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	792770	0	0
T9	282677	1189	0	0
T10	126796	8026	0	0
T11	41134	0	0	0
T12	11454	0	0	0
T13	41548	0	0	0
T14	0	10275	0	0
T23	0	393	0	0
T25	0	135	0	0
T26	0	19	0	0
T30	432	0	0	0
T33	290125	523	0	0
T36	0	2120	0	0
T39	0	5231	0	0
T43	0	2676	0	0
T44	136992	0	0	0
T50	9416	0	0	0
T55	8713	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	792770	0	0
T9	282677	1189	0	0
T10	126796	8026	0	0
T11	41134	0	0	0
T12	11454	0	0	0
T13	41548	0	0	0
T14	0	10275	0	0
T23	0	393	0	0
T25	0	135	0	0
T26	0	19	0	0
T30	432	0	0	0
T33	290125	523	0	0
T36	0	2120	0	0
T39	0	5231	0	0
T43	0	2676	0	0
T44	136992	0	0	0
T50	9416	0	0	0
T55	8713	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	120337255	0	0
T1	9756	9756	0	0
T2	8399	8304	0	0
T3	12502	12014	0	0
T4	8464	8464	0	0
T5	16	16	0	0
T6	89178	88954	0	0
T8	2097	0	0	0
T9	282677	279804	0	0
T10	126796	126346	0	0
T11	41134	0	0	0
T12	0	11454	0	0
T13	0	41296	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152304104	792770	0	0
T9	282677	1189	0	0
T10	126796	8026	0	0
T11	41134	0	0	0
T12	11454	0	0	0
T13	41548	0	0	0
T14	0	10275	0	0
T23	0	393	0	0
T25	0	135	0	0
T26	0	19	0	0
T30	432	0	0	0
T33	290125	523	0	0
T36	0	2120	0	0
T39	0	5231	0	0
T43	0	2676	0	0
T44	136992	0	0	0
T50	9416	0	0	0
T55	8713	0	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T9,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465656522	465572782	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	465656522	2268339	0	0
GntImpliesValid_A	465656522	2268339	0	0
GrantKnown_A	465656522	465572782	0	0
IdxKnown_A	465656522	465572782	0	0
IndexIsCorrect_A	465656522	2268339	0	0
LockArbDecision_A	465656522	0	0	0
NoReadyValidNoGrant_A	465656522	0	0	0
ReadyAndValidImplyGrant_A	465656522	2268339	0	0
ReqAndReadyImplyGrant_A	465656522	2268339	0	0
ReqImpliesValid_A	465656522	2268339	0	0
ReqStaysHighUntilGranted0_M	465656522	0	0	0
RoundRobin_A	465656522	8	0	954
ValidKnown_A	465656522	465572782	0	0
gen_data_port_assertion.DataFlow_A	465656522	2268339	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465656522	465572782	0	0
T1	32779	32722	0	0
T2	19828	19762	0	0
T3	19001	18905	0	0
T4	11037	10982	0	0
T5	7533	7434	0	0
T6	50788	50723	0	0
T7	819	762	0	0
T8	14935	14860	0	0
T9	375343	375254	0	0
T10	440723	440647	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465656522	2268339	0	0
T1	32779	832	0	0
T2	19828	832	0	0
T3	19001	832	0	0
T4	11037	832	0	0
T5	7533	832	0	0
T6	50788	832	0	0
T7	819	0	0	0
T8	14935	49	0	0
T9	375343	6069	0	0
T10	440723	12044	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465656522	2268339	0	0
T1	32779	832	0	0
T2	19828	832	0	0
T3	19001	832	0	0
T4	11037	832	0	0
T5	7533	832	0	0
T6	50788	832	0	0
T7	819	0	0	0
T8	14935	49	0	0
T9	375343	6069	0	0
T10	440723	12044	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465656522	465572782	0	0
T1	32779	32722	0	0
T2	19828	19762	0	0
T3	19001	18905	0	0
T4	11037	10982	0	0
T5	7533	7434	0	0
T6	50788	50723	0	0
T7	819	762	0	0
T8	14935	14860	0	0
T9	375343	375254	0	0
T10	440723	440647	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465656522	465572782	0	0
T1	32779	32722	0	0
T2	19828	19762	0	0
T3	19001	18905	0	0
T4	11037	10982	0	0
T5	7533	7434	0	0
T6	50788	50723	0	0
T7	819	762	0	0
T8	14935	14860	0	0
T9	375343	375254	0	0
T10	440723	440647	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465656522	2268339	0	0
T1	32779	832	0	0
T2	19828	832	0	0
T3	19001	832	0	0
T4	11037	832	0	0
T5	7533	832	0	0
T6	50788	832	0	0
T7	819	0	0	0
T8	14935	49	0	0
T9	375343	6069	0	0
T10	440723	12044	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465656522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465656522	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465656522	2268339	0	0
T1	32779	832	0	0
T2	19828	832	0	0
T3	19001	832	0	0
T4	11037	832	0	0
T5	7533	832	0	0
T6	50788	832	0	0
T7	819	0	0	0
T8	14935	49	0	0
T9	375343	6069	0	0
T10	440723	12044	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465656522	2268339	0	0
T1	32779	832	0	0
T2	19828	832	0	0
T3	19001	832	0	0
T4	11037	832	0	0
T5	7533	832	0	0
T6	50788	832	0	0
T7	819	0	0	0
T8	14935	49	0	0
T9	375343	6069	0	0
T10	440723	12044	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465656522	2268339	0	0
T1	32779	832	0	0
T2	19828	832	0	0
T3	19001	832	0	0
T4	11037	832	0	0
T5	7533	832	0	0
T6	50788	832	0	0
T7	819	0	0	0
T8	14935	49	0	0
T9	375343	6069	0	0
T10	440723	12044	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465656522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465656522	8	0	954
T15	345685	0	0	1
T49	598366	1	0	1
T52	237315	0	0	1
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	31005	0	0	1
T65	35675	0	0	1
T66	417976	0	0	1
T67	682716	0	0	1
T68	290539	0	0	1
T69	12052	0	0	1
T70	1289	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465656522	465572782	0	0
T1	32779	32722	0	0
T2	19828	19762	0	0
T3	19001	18905	0	0
T4	11037	10982	0	0
T5	7533	7434	0	0
T6	50788	50723	0	0
T7	819	762	0	0
T8	14935	14860	0	0
T9	375343	375254	0	0
T10	440723	440647	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465656522	2268339	0	0
T1	32779	832	0	0
T2	19828	832	0	0
T3	19001	832	0	0
T4	11037	832	0	0
T5	7533	832	0	0
T6	50788	832	0	0
T7	819	0	0	0
T8	14935	49	0	0
T9	375343	6069	0	0
T10	440723	12044	0	0
T12	0	832	0	0