Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
3831 |
0 |
0 |
T76 |
3366 |
9 |
0 |
0 |
T77 |
19155 |
2 |
0 |
0 |
T105 |
17464 |
309 |
0 |
0 |
T107 |
18592 |
2 |
0 |
0 |
T108 |
6127 |
214 |
0 |
0 |
T109 |
10988 |
99 |
0 |
0 |
T110 |
23619 |
251 |
0 |
0 |
T112 |
6967 |
125 |
0 |
0 |
T118 |
27494 |
4 |
0 |
0 |
T119 |
5098 |
3 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
1948 |
0 |
0 |
T123 |
8956 |
9 |
0 |
0 |
T129 |
78574 |
152 |
0 |
0 |
T143 |
6734 |
17 |
0 |
0 |
T144 |
4008 |
5 |
0 |
0 |
T155 |
2497 |
3 |
0 |
0 |
T156 |
34915 |
36 |
0 |
0 |
T157 |
271772 |
719 |
0 |
0 |
T158 |
33340 |
35 |
0 |
0 |
T159 |
12150 |
16 |
0 |
0 |
T160 |
7211 |
47 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
1906 |
0 |
0 |
T123 |
8956 |
11 |
0 |
0 |
T129 |
78574 |
118 |
0 |
0 |
T143 |
6734 |
23 |
0 |
0 |
T144 |
4008 |
4 |
0 |
0 |
T155 |
2497 |
6 |
0 |
0 |
T156 |
34915 |
28 |
0 |
0 |
T157 |
271772 |
676 |
0 |
0 |
T158 |
33340 |
34 |
0 |
0 |
T159 |
12150 |
13 |
0 |
0 |
T160 |
7211 |
70 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
2237 |
0 |
0 |
T123 |
8956 |
18 |
0 |
0 |
T129 |
78574 |
93 |
0 |
0 |
T144 |
4008 |
22 |
0 |
0 |
T156 |
34915 |
100 |
0 |
0 |
T157 |
271772 |
696 |
0 |
0 |
T158 |
33340 |
65 |
0 |
0 |
T159 |
12150 |
20 |
0 |
0 |
T160 |
7211 |
11 |
0 |
0 |
T161 |
7128 |
26 |
0 |
0 |
T162 |
10751 |
13 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
6066 |
0 |
0 |
T123 |
8956 |
132 |
0 |
0 |
T129 |
78574 |
111 |
0 |
0 |
T143 |
6734 |
8 |
0 |
0 |
T144 |
4008 |
2 |
0 |
0 |
T155 |
2497 |
2 |
0 |
0 |
T156 |
34915 |
607 |
0 |
0 |
T157 |
271772 |
729 |
0 |
0 |
T158 |
33340 |
432 |
0 |
0 |
T159 |
12150 |
142 |
0 |
0 |
T160 |
7211 |
16 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
5962 |
0 |
0 |
T123 |
8956 |
7 |
0 |
0 |
T129 |
78574 |
143 |
0 |
0 |
T143 |
6734 |
25 |
0 |
0 |
T144 |
4008 |
114 |
0 |
0 |
T155 |
2497 |
1 |
0 |
0 |
T156 |
34915 |
507 |
0 |
0 |
T157 |
271772 |
683 |
0 |
0 |
T158 |
33340 |
594 |
0 |
0 |
T159 |
12150 |
260 |
0 |
0 |
T160 |
7211 |
20 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
6434 |
0 |
0 |
T123 |
8956 |
10 |
0 |
0 |
T129 |
78574 |
141 |
0 |
0 |
T143 |
6734 |
23 |
0 |
0 |
T144 |
4008 |
2 |
0 |
0 |
T156 |
34915 |
518 |
0 |
0 |
T157 |
271772 |
686 |
0 |
0 |
T158 |
33340 |
593 |
0 |
0 |
T159 |
12150 |
253 |
0 |
0 |
T160 |
7211 |
20 |
0 |
0 |
T161 |
7128 |
5 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
6092 |
0 |
0 |
T123 |
8956 |
216 |
0 |
0 |
T129 |
78574 |
129 |
0 |
0 |
T143 |
6734 |
18 |
0 |
0 |
T144 |
4008 |
1 |
0 |
0 |
T155 |
2497 |
4 |
0 |
0 |
T156 |
34915 |
462 |
0 |
0 |
T157 |
271772 |
714 |
0 |
0 |
T158 |
33340 |
626 |
0 |
0 |
T159 |
12150 |
353 |
0 |
0 |
T160 |
7211 |
11 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
7112 |
0 |
0 |
T123 |
8956 |
118 |
0 |
0 |
T129 |
78574 |
109 |
0 |
0 |
T143 |
6734 |
19 |
0 |
0 |
T144 |
4008 |
1 |
0 |
0 |
T155 |
2497 |
4 |
0 |
0 |
T156 |
34915 |
609 |
0 |
0 |
T157 |
271772 |
704 |
0 |
0 |
T158 |
33340 |
917 |
0 |
0 |
T159 |
12150 |
279 |
0 |
0 |
T161 |
7128 |
14 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
7202 |
0 |
0 |
T123 |
8956 |
148 |
0 |
0 |
T129 |
78574 |
144 |
0 |
0 |
T143 |
6734 |
32 |
0 |
0 |
T144 |
4008 |
126 |
0 |
0 |
T155 |
2497 |
4 |
0 |
0 |
T156 |
34915 |
866 |
0 |
0 |
T157 |
271772 |
686 |
0 |
0 |
T158 |
33340 |
463 |
0 |
0 |
T159 |
12150 |
170 |
0 |
0 |
T160 |
7211 |
7 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
6719 |
0 |
0 |
T123 |
8956 |
80 |
0 |
0 |
T129 |
78574 |
143 |
0 |
0 |
T143 |
6734 |
5 |
0 |
0 |
T144 |
4008 |
4 |
0 |
0 |
T155 |
2497 |
1 |
0 |
0 |
T156 |
34915 |
803 |
0 |
0 |
T157 |
271772 |
643 |
0 |
0 |
T158 |
33340 |
657 |
0 |
0 |
T159 |
12150 |
122 |
0 |
0 |
T160 |
7211 |
52 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
6286 |
0 |
0 |
T123 |
8956 |
272 |
0 |
0 |
T129 |
78574 |
106 |
0 |
0 |
T143 |
6734 |
14 |
0 |
0 |
T144 |
4008 |
1 |
0 |
0 |
T155 |
2497 |
2 |
0 |
0 |
T156 |
34915 |
272 |
0 |
0 |
T157 |
271772 |
697 |
0 |
0 |
T158 |
33340 |
641 |
0 |
0 |
T159 |
12150 |
397 |
0 |
0 |
T160 |
7211 |
20 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
3862 |
0 |
0 |
T123 |
8956 |
47 |
0 |
0 |
T129 |
78574 |
116 |
0 |
0 |
T143 |
6734 |
12 |
0 |
0 |
T144 |
4008 |
2 |
0 |
0 |
T155 |
2497 |
1 |
0 |
0 |
T156 |
34915 |
353 |
0 |
0 |
T157 |
271772 |
670 |
0 |
0 |
T158 |
33340 |
229 |
0 |
0 |
T159 |
12150 |
93 |
0 |
0 |
T160 |
7211 |
16 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
4196 |
0 |
0 |
T123 |
8956 |
120 |
0 |
0 |
T129 |
78574 |
186 |
0 |
0 |
T143 |
6734 |
14 |
0 |
0 |
T144 |
4008 |
45 |
0 |
0 |
T155 |
2497 |
3 |
0 |
0 |
T156 |
34915 |
159 |
0 |
0 |
T157 |
271772 |
685 |
0 |
0 |
T158 |
33340 |
341 |
0 |
0 |
T159 |
12150 |
105 |
0 |
0 |
T160 |
7211 |
37 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
3716 |
0 |
0 |
T110 |
23619 |
1 |
0 |
0 |
T123 |
8956 |
45 |
0 |
0 |
T129 |
78574 |
124 |
0 |
0 |
T144 |
4008 |
2 |
0 |
0 |
T155 |
2497 |
2 |
0 |
0 |
T156 |
34915 |
322 |
0 |
0 |
T157 |
271772 |
698 |
0 |
0 |
T158 |
33340 |
194 |
0 |
0 |
T159 |
12150 |
55 |
0 |
0 |
T160 |
7211 |
17 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
3550 |
0 |
0 |
T123 |
8956 |
51 |
0 |
0 |
T129 |
78574 |
85 |
0 |
0 |
T143 |
6734 |
32 |
0 |
0 |
T144 |
4008 |
64 |
0 |
0 |
T155 |
2497 |
2 |
0 |
0 |
T156 |
34915 |
334 |
0 |
0 |
T157 |
271772 |
693 |
0 |
0 |
T158 |
33340 |
293 |
0 |
0 |
T159 |
12150 |
47 |
0 |
0 |
T160 |
7211 |
26 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
4034 |
0 |
0 |
T123 |
8956 |
125 |
0 |
0 |
T129 |
78574 |
133 |
0 |
0 |
T144 |
4008 |
42 |
0 |
0 |
T155 |
2497 |
8 |
0 |
0 |
T156 |
34915 |
322 |
0 |
0 |
T157 |
271772 |
682 |
0 |
0 |
T158 |
33340 |
329 |
0 |
0 |
T159 |
12150 |
4 |
0 |
0 |
T160 |
7211 |
3 |
0 |
0 |
T161 |
7128 |
11 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
3620 |
0 |
0 |
T123 |
8956 |
13 |
0 |
0 |
T129 |
78574 |
156 |
0 |
0 |
T143 |
6734 |
3 |
0 |
0 |
T144 |
4008 |
3 |
0 |
0 |
T155 |
2497 |
8 |
0 |
0 |
T156 |
34915 |
233 |
0 |
0 |
T157 |
271772 |
699 |
0 |
0 |
T158 |
33340 |
382 |
0 |
0 |
T159 |
12150 |
48 |
0 |
0 |
T161 |
7128 |
2 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
3713 |
0 |
0 |
T123 |
8956 |
45 |
0 |
0 |
T129 |
78574 |
139 |
0 |
0 |
T143 |
6734 |
6 |
0 |
0 |
T144 |
4008 |
1 |
0 |
0 |
T155 |
2497 |
1 |
0 |
0 |
T156 |
34915 |
244 |
0 |
0 |
T157 |
271772 |
678 |
0 |
0 |
T158 |
33340 |
316 |
0 |
0 |
T159 |
12150 |
99 |
0 |
0 |
T160 |
7211 |
37 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
3662 |
0 |
0 |
T123 |
8956 |
120 |
0 |
0 |
T129 |
78574 |
151 |
0 |
0 |
T143 |
6734 |
11 |
0 |
0 |
T144 |
4008 |
28 |
0 |
0 |
T155 |
2497 |
6 |
0 |
0 |
T156 |
34915 |
207 |
0 |
0 |
T157 |
271772 |
667 |
0 |
0 |
T158 |
33340 |
292 |
0 |
0 |
T159 |
12150 |
42 |
0 |
0 |
T160 |
7211 |
51 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
3943 |
0 |
0 |
T110 |
23619 |
1 |
0 |
0 |
T123 |
8956 |
59 |
0 |
0 |
T129 |
78574 |
92 |
0 |
0 |
T143 |
6734 |
9 |
0 |
0 |
T144 |
4008 |
47 |
0 |
0 |
T155 |
2497 |
9 |
0 |
0 |
T156 |
34915 |
392 |
0 |
0 |
T157 |
271772 |
727 |
0 |
0 |
T158 |
33340 |
299 |
0 |
0 |
T159 |
12150 |
55 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
3423 |
0 |
0 |
T112 |
6967 |
4 |
0 |
0 |
T123 |
8956 |
43 |
0 |
0 |
T129 |
78574 |
118 |
0 |
0 |
T143 |
6734 |
1 |
0 |
0 |
T144 |
4008 |
6 |
0 |
0 |
T155 |
2497 |
6 |
0 |
0 |
T156 |
34915 |
354 |
0 |
0 |
T157 |
271772 |
671 |
0 |
0 |
T158 |
33340 |
248 |
0 |
0 |
T159 |
12150 |
84 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
3802 |
0 |
0 |
T123 |
8956 |
46 |
0 |
0 |
T129 |
78574 |
157 |
0 |
0 |
T143 |
6734 |
29 |
0 |
0 |
T144 |
4008 |
5 |
0 |
0 |
T155 |
2497 |
1 |
0 |
0 |
T156 |
34915 |
391 |
0 |
0 |
T157 |
271772 |
694 |
0 |
0 |
T158 |
33340 |
287 |
0 |
0 |
T159 |
12150 |
107 |
0 |
0 |
T160 |
7211 |
40 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
4035 |
0 |
0 |
T123 |
8956 |
105 |
0 |
0 |
T129 |
78574 |
122 |
0 |
0 |
T143 |
6734 |
3 |
0 |
0 |
T144 |
4008 |
2 |
0 |
0 |
T155 |
2497 |
6 |
0 |
0 |
T156 |
34915 |
412 |
0 |
0 |
T157 |
271772 |
736 |
0 |
0 |
T158 |
33340 |
260 |
0 |
0 |
T159 |
12150 |
57 |
0 |
0 |
T160 |
7211 |
6 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
3760 |
0 |
0 |
T123 |
8956 |
62 |
0 |
0 |
T129 |
78574 |
200 |
0 |
0 |
T143 |
6734 |
7 |
0 |
0 |
T144 |
4008 |
51 |
0 |
0 |
T156 |
34915 |
254 |
0 |
0 |
T157 |
271772 |
637 |
0 |
0 |
T158 |
33340 |
283 |
0 |
0 |
T159 |
12150 |
97 |
0 |
0 |
T160 |
7211 |
4 |
0 |
0 |
T162 |
10751 |
63 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
3875 |
0 |
0 |
T123 |
8956 |
115 |
0 |
0 |
T129 |
78574 |
102 |
0 |
0 |
T143 |
6734 |
13 |
0 |
0 |
T144 |
4008 |
46 |
0 |
0 |
T155 |
2497 |
10 |
0 |
0 |
T156 |
34915 |
218 |
0 |
0 |
T157 |
271772 |
709 |
0 |
0 |
T158 |
33340 |
182 |
0 |
0 |
T159 |
12150 |
117 |
0 |
0 |
T160 |
7211 |
27 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
3950 |
0 |
0 |
T123 |
8956 |
14 |
0 |
0 |
T129 |
78574 |
111 |
0 |
0 |
T143 |
6734 |
5 |
0 |
0 |
T155 |
2497 |
2 |
0 |
0 |
T156 |
34915 |
325 |
0 |
0 |
T157 |
271772 |
673 |
0 |
0 |
T158 |
33340 |
313 |
0 |
0 |
T159 |
12150 |
67 |
0 |
0 |
T160 |
7211 |
47 |
0 |
0 |
T161 |
7128 |
17 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
3724 |
0 |
0 |
T123 |
8956 |
33 |
0 |
0 |
T129 |
78574 |
126 |
0 |
0 |
T143 |
6734 |
24 |
0 |
0 |
T144 |
4008 |
49 |
0 |
0 |
T155 |
2497 |
3 |
0 |
0 |
T156 |
34915 |
366 |
0 |
0 |
T157 |
271772 |
632 |
0 |
0 |
T158 |
33340 |
171 |
0 |
0 |
T159 |
12150 |
124 |
0 |
0 |
T160 |
7211 |
15 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
3463 |
0 |
0 |
T113 |
16264 |
1 |
0 |
0 |
T123 |
8956 |
61 |
0 |
0 |
T129 |
78574 |
125 |
0 |
0 |
T144 |
4008 |
54 |
0 |
0 |
T155 |
2497 |
4 |
0 |
0 |
T156 |
34915 |
314 |
0 |
0 |
T157 |
271772 |
615 |
0 |
0 |
T158 |
33340 |
197 |
0 |
0 |
T159 |
12150 |
166 |
0 |
0 |
T161 |
7128 |
27 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
3720 |
0 |
0 |
T123 |
8956 |
132 |
0 |
0 |
T129 |
78574 |
118 |
0 |
0 |
T143 |
6734 |
13 |
0 |
0 |
T144 |
4008 |
63 |
0 |
0 |
T155 |
2497 |
1 |
0 |
0 |
T156 |
34915 |
341 |
0 |
0 |
T157 |
271772 |
663 |
0 |
0 |
T158 |
33340 |
267 |
0 |
0 |
T159 |
12150 |
17 |
0 |
0 |
T160 |
7211 |
1 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
3753 |
0 |
0 |
T123 |
8956 |
44 |
0 |
0 |
T129 |
78574 |
160 |
0 |
0 |
T143 |
6734 |
13 |
0 |
0 |
T144 |
4008 |
7 |
0 |
0 |
T155 |
2497 |
2 |
0 |
0 |
T156 |
34915 |
334 |
0 |
0 |
T157 |
271772 |
739 |
0 |
0 |
T158 |
33340 |
279 |
0 |
0 |
T159 |
12150 |
58 |
0 |
0 |
T160 |
7211 |
7 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
3745 |
0 |
0 |
T113 |
16264 |
3 |
0 |
0 |
T123 |
8956 |
16 |
0 |
0 |
T129 |
78574 |
111 |
0 |
0 |
T143 |
6734 |
18 |
0 |
0 |
T144 |
4008 |
6 |
0 |
0 |
T156 |
34915 |
309 |
0 |
0 |
T157 |
271772 |
682 |
0 |
0 |
T158 |
33340 |
243 |
0 |
0 |
T159 |
12150 |
126 |
0 |
0 |
T160 |
7211 |
13 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
4098 |
0 |
0 |
T123 |
8956 |
68 |
0 |
0 |
T129 |
78574 |
131 |
0 |
0 |
T143 |
6734 |
21 |
0 |
0 |
T144 |
4008 |
53 |
0 |
0 |
T156 |
34915 |
451 |
0 |
0 |
T157 |
271772 |
653 |
0 |
0 |
T158 |
33340 |
322 |
0 |
0 |
T159 |
12150 |
60 |
0 |
0 |
T160 |
7211 |
36 |
0 |
0 |
T161 |
7128 |
19 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
4096 |
0 |
0 |
T123 |
8956 |
108 |
0 |
0 |
T129 |
78574 |
92 |
0 |
0 |
T143 |
6734 |
2 |
0 |
0 |
T144 |
4008 |
52 |
0 |
0 |
T155 |
2497 |
4 |
0 |
0 |
T156 |
34915 |
309 |
0 |
0 |
T157 |
271772 |
709 |
0 |
0 |
T158 |
33340 |
220 |
0 |
0 |
T159 |
12150 |
104 |
0 |
0 |
T160 |
7211 |
24 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
3748 |
0 |
0 |
T123 |
8956 |
142 |
0 |
0 |
T129 |
78574 |
145 |
0 |
0 |
T143 |
6734 |
6 |
0 |
0 |
T144 |
4008 |
50 |
0 |
0 |
T155 |
2497 |
9 |
0 |
0 |
T156 |
34915 |
166 |
0 |
0 |
T157 |
271772 |
685 |
0 |
0 |
T158 |
33340 |
305 |
0 |
0 |
T159 |
12150 |
104 |
0 |
0 |
T160 |
7211 |
21 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
3530 |
0 |
0 |
T123 |
8956 |
158 |
0 |
0 |
T129 |
78574 |
120 |
0 |
0 |
T143 |
6734 |
15 |
0 |
0 |
T144 |
4008 |
4 |
0 |
0 |
T155 |
2497 |
1 |
0 |
0 |
T156 |
34915 |
204 |
0 |
0 |
T157 |
271772 |
680 |
0 |
0 |
T158 |
33340 |
193 |
0 |
0 |
T159 |
12150 |
116 |
0 |
0 |
T160 |
7211 |
39 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
1934 |
0 |
0 |
T110 |
23619 |
1 |
0 |
0 |
T123 |
8956 |
11 |
0 |
0 |
T129 |
78574 |
107 |
0 |
0 |
T143 |
6734 |
12 |
0 |
0 |
T155 |
2497 |
3 |
0 |
0 |
T156 |
34915 |
51 |
0 |
0 |
T157 |
271772 |
640 |
0 |
0 |
T158 |
33340 |
44 |
0 |
0 |
T159 |
12150 |
24 |
0 |
0 |
T160 |
7211 |
35 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
2085 |
0 |
0 |
T123 |
8956 |
13 |
0 |
0 |
T129 |
78574 |
144 |
0 |
0 |
T143 |
6734 |
18 |
0 |
0 |
T144 |
4008 |
14 |
0 |
0 |
T155 |
2497 |
5 |
0 |
0 |
T156 |
34915 |
47 |
0 |
0 |
T157 |
271772 |
701 |
0 |
0 |
T158 |
33340 |
53 |
0 |
0 |
T159 |
12150 |
14 |
0 |
0 |
T160 |
7211 |
3 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
2162 |
0 |
0 |
T123 |
8956 |
26 |
0 |
0 |
T129 |
78574 |
118 |
0 |
0 |
T143 |
6734 |
29 |
0 |
0 |
T144 |
4008 |
4 |
0 |
0 |
T156 |
34915 |
69 |
0 |
0 |
T157 |
271772 |
752 |
0 |
0 |
T158 |
33340 |
51 |
0 |
0 |
T159 |
12150 |
20 |
0 |
0 |
T160 |
7211 |
12 |
0 |
0 |
T161 |
7128 |
9 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
2100 |
0 |
0 |
T123 |
8956 |
14 |
0 |
0 |
T129 |
78574 |
132 |
0 |
0 |
T143 |
6734 |
13 |
0 |
0 |
T144 |
4008 |
10 |
0 |
0 |
T155 |
2497 |
8 |
0 |
0 |
T156 |
34915 |
54 |
0 |
0 |
T157 |
271772 |
735 |
0 |
0 |
T158 |
33340 |
58 |
0 |
0 |
T159 |
12150 |
16 |
0 |
0 |
T160 |
7211 |
13 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
2183 |
0 |
0 |
T123 |
8956 |
25 |
0 |
0 |
T129 |
78574 |
140 |
0 |
0 |
T143 |
6734 |
16 |
0 |
0 |
T155 |
2497 |
2 |
0 |
0 |
T156 |
34915 |
120 |
0 |
0 |
T157 |
271772 |
599 |
0 |
0 |
T158 |
33340 |
73 |
0 |
0 |
T159 |
12150 |
34 |
0 |
0 |
T160 |
7211 |
3 |
0 |
0 |
T161 |
7128 |
54 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
3963 |
0 |
0 |
T14 |
405832 |
16 |
0 |
0 |
T18 |
0 |
13 |
0 |
0 |
T19 |
0 |
62 |
0 |
0 |
T22 |
0 |
80 |
0 |
0 |
T23 |
544009 |
0 |
0 |
0 |
T24 |
37607 |
0 |
0 |
0 |
T25 |
139830 |
0 |
0 |
0 |
T26 |
356019 |
0 |
0 |
0 |
T27 |
146915 |
0 |
0 |
0 |
T28 |
8275 |
0 |
0 |
0 |
T29 |
25336 |
0 |
0 |
0 |
T37 |
0 |
20 |
0 |
0 |
T38 |
639 |
0 |
0 |
0 |
T39 |
200421 |
0 |
0 |
0 |
T59 |
0 |
44 |
0 |
0 |
T163 |
0 |
29 |
0 |
0 |
T164 |
0 |
9 |
0 |
0 |
T165 |
0 |
37 |
0 |
0 |
T166 |
0 |
40 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
2024 |
0 |
0 |
T113 |
16264 |
9 |
0 |
0 |
T123 |
8956 |
25 |
0 |
0 |
T129 |
78574 |
129 |
0 |
0 |
T143 |
6734 |
22 |
0 |
0 |
T144 |
4008 |
6 |
0 |
0 |
T155 |
2497 |
3 |
0 |
0 |
T156 |
34915 |
79 |
0 |
0 |
T157 |
271772 |
735 |
0 |
0 |
T158 |
33340 |
69 |
0 |
0 |
T159 |
12150 |
16 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
2025 |
0 |
0 |
T123 |
8956 |
25 |
0 |
0 |
T129 |
78574 |
90 |
0 |
0 |
T143 |
6734 |
24 |
0 |
0 |
T144 |
4008 |
1 |
0 |
0 |
T155 |
2497 |
3 |
0 |
0 |
T156 |
34915 |
57 |
0 |
0 |
T157 |
271772 |
630 |
0 |
0 |
T158 |
33340 |
70 |
0 |
0 |
T159 |
12150 |
19 |
0 |
0 |
T160 |
7211 |
16 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
1983 |
0 |
0 |
T123 |
8956 |
9 |
0 |
0 |
T129 |
78574 |
131 |
0 |
0 |
T143 |
6734 |
19 |
0 |
0 |
T144 |
4008 |
8 |
0 |
0 |
T155 |
2497 |
6 |
0 |
0 |
T156 |
34915 |
29 |
0 |
0 |
T157 |
271772 |
736 |
0 |
0 |
T158 |
33340 |
43 |
0 |
0 |
T159 |
12150 |
6 |
0 |
0 |
T160 |
7211 |
13 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
1910 |
0 |
0 |
T123 |
8956 |
13 |
0 |
0 |
T129 |
78574 |
134 |
0 |
0 |
T143 |
6734 |
1 |
0 |
0 |
T144 |
4008 |
9 |
0 |
0 |
T155 |
2497 |
9 |
0 |
0 |
T156 |
34915 |
31 |
0 |
0 |
T157 |
271772 |
728 |
0 |
0 |
T158 |
33340 |
42 |
0 |
0 |
T159 |
12150 |
10 |
0 |
0 |
T160 |
7211 |
47 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
1969 |
0 |
0 |
T123 |
8956 |
14 |
0 |
0 |
T129 |
78574 |
140 |
0 |
0 |
T143 |
6734 |
14 |
0 |
0 |
T144 |
4008 |
2 |
0 |
0 |
T155 |
2497 |
6 |
0 |
0 |
T156 |
34915 |
35 |
0 |
0 |
T157 |
271772 |
656 |
0 |
0 |
T158 |
33340 |
55 |
0 |
0 |
T159 |
12150 |
11 |
0 |
0 |
T160 |
7211 |
3 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
1924 |
0 |
0 |
T123 |
8956 |
13 |
0 |
0 |
T129 |
78574 |
139 |
0 |
0 |
T144 |
4008 |
1 |
0 |
0 |
T156 |
34915 |
33 |
0 |
0 |
T157 |
271772 |
688 |
0 |
0 |
T158 |
33340 |
44 |
0 |
0 |
T159 |
12150 |
7 |
0 |
0 |
T160 |
7211 |
3 |
0 |
0 |
T161 |
7128 |
49 |
0 |
0 |
T162 |
10751 |
18 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
2208 |
0 |
0 |
T123 |
8956 |
42 |
0 |
0 |
T129 |
78574 |
148 |
0 |
0 |
T143 |
6734 |
9 |
0 |
0 |
T144 |
4008 |
3 |
0 |
0 |
T155 |
2497 |
4 |
0 |
0 |
T156 |
34915 |
103 |
0 |
0 |
T157 |
271772 |
637 |
0 |
0 |
T158 |
33340 |
70 |
0 |
0 |
T159 |
12150 |
33 |
0 |
0 |
T160 |
7211 |
32 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
1835 |
0 |
0 |
T110 |
23619 |
1 |
0 |
0 |
T123 |
8956 |
6 |
0 |
0 |
T129 |
78574 |
103 |
0 |
0 |
T143 |
6734 |
13 |
0 |
0 |
T155 |
2497 |
3 |
0 |
0 |
T156 |
34915 |
53 |
0 |
0 |
T157 |
271772 |
658 |
0 |
0 |
T158 |
33340 |
41 |
0 |
0 |
T159 |
12150 |
16 |
0 |
0 |
T160 |
7211 |
1 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
2462 |
0 |
0 |
T123 |
8956 |
42 |
0 |
0 |
T129 |
78574 |
134 |
0 |
0 |
T143 |
6734 |
8 |
0 |
0 |
T144 |
4008 |
5 |
0 |
0 |
T155 |
2497 |
3 |
0 |
0 |
T156 |
34915 |
67 |
0 |
0 |
T157 |
271772 |
617 |
0 |
0 |
T158 |
33340 |
140 |
0 |
0 |
T159 |
12150 |
54 |
0 |
0 |
T167 |
9523 |
6 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
2158 |
0 |
0 |
T123 |
8956 |
26 |
0 |
0 |
T129 |
78574 |
126 |
0 |
0 |
T143 |
6734 |
13 |
0 |
0 |
T144 |
4008 |
7 |
0 |
0 |
T155 |
2497 |
6 |
0 |
0 |
T156 |
34915 |
66 |
0 |
0 |
T157 |
271772 |
683 |
0 |
0 |
T158 |
33340 |
62 |
0 |
0 |
T159 |
12150 |
21 |
0 |
0 |
T160 |
7211 |
43 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
2057 |
0 |
0 |
T123 |
8956 |
16 |
0 |
0 |
T129 |
78574 |
104 |
0 |
0 |
T143 |
6734 |
9 |
0 |
0 |
T144 |
4008 |
7 |
0 |
0 |
T155 |
2497 |
7 |
0 |
0 |
T156 |
34915 |
39 |
0 |
0 |
T157 |
271772 |
672 |
0 |
0 |
T158 |
33340 |
44 |
0 |
0 |
T159 |
12150 |
4 |
0 |
0 |
T160 |
7211 |
37 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
1940 |
0 |
0 |
T123 |
8956 |
15 |
0 |
0 |
T129 |
78574 |
187 |
0 |
0 |
T143 |
6734 |
18 |
0 |
0 |
T144 |
4008 |
1 |
0 |
0 |
T156 |
34915 |
30 |
0 |
0 |
T157 |
271772 |
761 |
0 |
0 |
T158 |
33340 |
44 |
0 |
0 |
T159 |
12150 |
6 |
0 |
0 |
T160 |
7211 |
8 |
0 |
0 |
T161 |
7128 |
26 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
1888 |
0 |
0 |
T123 |
8956 |
18 |
0 |
0 |
T129 |
78574 |
119 |
0 |
0 |
T143 |
6734 |
16 |
0 |
0 |
T144 |
4008 |
6 |
0 |
0 |
T155 |
2497 |
1 |
0 |
0 |
T156 |
34915 |
44 |
0 |
0 |
T157 |
271772 |
710 |
0 |
0 |
T158 |
33340 |
33 |
0 |
0 |
T159 |
12150 |
4 |
0 |
0 |
T160 |
7211 |
6 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
1958 |
0 |
0 |
T123 |
8956 |
2 |
0 |
0 |
T129 |
78574 |
153 |
0 |
0 |
T143 |
6734 |
30 |
0 |
0 |
T144 |
4008 |
2 |
0 |
0 |
T155 |
2497 |
6 |
0 |
0 |
T156 |
34915 |
51 |
0 |
0 |
T157 |
271772 |
669 |
0 |
0 |
T158 |
33340 |
42 |
0 |
0 |
T159 |
12150 |
18 |
0 |
0 |
T160 |
7211 |
18 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
1819 |
0 |
0 |
T123 |
8956 |
3 |
0 |
0 |
T129 |
78574 |
129 |
0 |
0 |
T143 |
6734 |
17 |
0 |
0 |
T144 |
4008 |
6 |
0 |
0 |
T155 |
2497 |
6 |
0 |
0 |
T156 |
34915 |
51 |
0 |
0 |
T157 |
271772 |
664 |
0 |
0 |
T158 |
33340 |
45 |
0 |
0 |
T159 |
12150 |
16 |
0 |
0 |
T160 |
7211 |
34 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
467925003 |
1811 |
0 |
0 |
T123 |
8956 |
19 |
0 |
0 |
T129 |
78574 |
125 |
0 |
0 |
T143 |
6734 |
5 |
0 |
0 |
T155 |
2497 |
6 |
0 |
0 |
T156 |
34915 |
47 |
0 |
0 |
T157 |
271772 |
638 |
0 |
0 |
T158 |
33340 |
31 |
0 |
0 |
T159 |
12150 |
6 |
0 |
0 |
T160 |
7211 |
42 |
0 |
0 |
T161 |
7128 |
37 |
0 |
0 |