Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3815460	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4349457

1

T1

4

T2

19720

T3

3545

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4591115	1			T1	1		T2	19477		T3	6802
values[0x0]	1787570	1			T1	10		T2	10020		T3	1739
values[0x1]	1786232	1			T1	4		T2	9818		T3	1672

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2706739	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5458178

1

T1

4

T2

25776

T3

5636

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28905	1			T2	132		T9	4		T10	2
valid_sources[0x01]	30560	1			T2	131		T3	914		T9	1
valid_sources[0x02]	28589	1			T2	157		T9	1		T10	4
valid_sources[0x03]	29909	1			T2	182		T3	3		T6	1
valid_sources[0x04]	29601	1			T2	197		T9	1		T10	9
valid_sources[0x05]	29234	1			T2	113		T3	204		T9	5
valid_sources[0x06]	27815	1			T2	175		T9	1		T10	15
valid_sources[0x07]	29825	1			T2	149		T9	7		T10	17
valid_sources[0x08]	31654	1			T2	141		T3	212		T8	1
valid_sources[0x09]	29807	1			T2	233		T9	4		T10	6
valid_sources[0x0a]	29226	1			T2	145		T9	3		T10	5
valid_sources[0x0b]	32615	1			T2	150		T3	272		T9	2
valid_sources[0x0c]	29647	1			T2	127		T3	4		T9	7
valid_sources[0x0d]	29623	1			T2	97		T9	2		T10	2
valid_sources[0x0e]	31735	1			T2	196		T3	482		T9	6
valid_sources[0x0f]	30059	1			T2	167		T9	5		T10	18
valid_sources[0x10]	57018	1			T2	123		T6	1		T9	1
valid_sources[0x11]	29292	1			T2	139		T9	5		T10	10
valid_sources[0x12]	30310	1			T2	176		T3	1		T8	1
valid_sources[0x13]	55295	1			T2	172		T9	3		T10	5
valid_sources[0x14]	30388	1			T2	177		T9	2		T10	8
valid_sources[0x15]	29803	1			T2	204		T9	3		T10	15
valid_sources[0x16]	32477	1			T2	181		T6	1		T10	14
valid_sources[0x17]	31841	1			T2	185		T3	1		T9	2
valid_sources[0x18]	31052	1			T2	172		T9	4		T10	8
valid_sources[0x19]	31807	1			T2	128		T3	38		T5	1
valid_sources[0x1a]	30758	1			T2	169		T9	1		T10	12
valid_sources[0x1b]	30092	1			T2	138		T9	5		T10	6
valid_sources[0x1c]	31809	1			T2	118		T10	9		T15	154
valid_sources[0x1d]	30725	1			T2	147		T9	2		T10	16
valid_sources[0x1e]	30297	1			T2	127		T9	3		T10	8
valid_sources[0x1f]	30417	1			T2	206		T3	2		T9	5
valid_sources[0x20]	55710	1			T2	115		T9	3		T10	14
valid_sources[0x21]	37011	1			T2	169		T9	4		T10	9
valid_sources[0x22]	30207	1			T2	154		T9	1		T10	6
valid_sources[0x23]	30642	1			T2	131		T9	4		T10	7
valid_sources[0x24]	29535	1			T2	176		T3	2		T9	4
valid_sources[0x25]	29981	1			T2	175		T3	38		T9	5
valid_sources[0x26]	31443	1			T2	200		T3	175		T9	2
valid_sources[0x27]	29412	1			T2	166		T3	73		T9	3
valid_sources[0x28]	29031	1			T2	199		T3	520		T9	9
valid_sources[0x29]	29983	1			T2	214		T9	1		T10	8
valid_sources[0x2a]	29565	1			T2	188		T3	9		T9	3
valid_sources[0x2b]	28521	1			T2	159		T9	5		T10	8
valid_sources[0x2c]	32829	1			T2	184		T3	113		T9	4
valid_sources[0x2d]	33321	1			T2	134		T6	1		T9	8
valid_sources[0x2e]	29691	1			T2	166		T9	2		T10	11
valid_sources[0x2f]	30185	1			T2	188		T3	2		T8	1
valid_sources[0x30]	33160	1			T2	201		T9	7		T10	8
valid_sources[0x31]	36512	1			T2	116		T5	1128		T9	3
valid_sources[0x32]	29917	1			T2	162		T10	19		T58	5
valid_sources[0x33]	32471	1			T2	149		T9	1		T10	1
valid_sources[0x34]	29456	1			T2	166		T3	1		T9	2
valid_sources[0x35]	29318	1			T2	177		T9	2		T10	14
valid_sources[0x36]	32559	1			T2	144		T3	268		T9	5
valid_sources[0x37]	90917	1			T2	150		T5	1		T9	4
valid_sources[0x38]	33983	1			T2	154		T3	5		T9	2
valid_sources[0x39]	35557	1			T2	150		T3	159		T9	2
valid_sources[0x3a]	28805	1			T2	156		T9	4		T10	8
valid_sources[0x3b]	31868	1			T2	132		T9	3		T10	10
valid_sources[0x3c]	34921	1			T2	129		T8	1		T9	3
valid_sources[0x3d]	31877	1			T2	185		T3	1		T9	5
valid_sources[0x3e]	30355	1			T2	146		T9	5		T10	3
valid_sources[0x3f]	29740	1			T2	114		T9	2		T10	6
valid_sources[0x40]	28529	1			T2	152		T9	1		T10	8
valid_sources[0x41]	28780	1			T2	134		T9	1		T10	7
valid_sources[0x42]	30171	1			T2	89		T3	1		T9	6
valid_sources[0x43]	29727	1			T2	119		T9	3		T10	3
valid_sources[0x44]	39652	1			T2	145		T3	136		T9	4
valid_sources[0x45]	29290	1			T2	120		T9	6		T10	4
valid_sources[0x46]	31228	1			T2	179		T3	95		T9	4
valid_sources[0x47]	29387	1			T2	119		T3	19		T9	6
valid_sources[0x48]	33331	1			T2	234		T3	10		T6	2
valid_sources[0x49]	33607	1			T2	151		T9	3		T10	10
valid_sources[0x4a]	30773	1			T2	151		T3	1		T6	2
valid_sources[0x4b]	35259	1			T2	133		T9	5		T10	7
valid_sources[0x4c]	31018	1			T2	127		T9	3		T10	6
valid_sources[0x4d]	28637	1			T2	150		T3	41		T9	2
valid_sources[0x4e]	26822	1			T2	132		T3	1		T9	5
valid_sources[0x4f]	29242	1			T2	184		T9	5		T10	10
valid_sources[0x50]	29979	1			T2	201		T9	4		T10	10
valid_sources[0x51]	31397	1			T2	88		T5	1		T9	4
valid_sources[0x52]	31619	1			T2	86		T9	1		T10	6
valid_sources[0x53]	28005	1			T2	151		T9	8		T10	9
valid_sources[0x54]	28517	1			T2	133		T9	10		T10	16
valid_sources[0x55]	29238	1			T2	123		T6	1		T9	1
valid_sources[0x56]	29792	1			T2	157		T3	1		T9	3
valid_sources[0x57]	31279	1			T2	134		T9	2		T10	14
valid_sources[0x58]	36412	1			T2	144		T3	227		T9	3
valid_sources[0x59]	30516	1			T2	121		T3	4		T9	6
valid_sources[0x5a]	29468	1			T2	118		T3	430		T9	6
valid_sources[0x5b]	31405	1			T2	156		T3	3		T9	3
valid_sources[0x5c]	30892	1			T2	177		T9	1		T10	10
valid_sources[0x5d]	29559	1			T2	121		T9	3		T10	8
valid_sources[0x5e]	31693	1			T2	100		T3	3		T9	1
valid_sources[0x5f]	33425	1			T2	189		T8	1		T9	2
valid_sources[0x60]	33383	1			T2	143		T9	5		T10	12
valid_sources[0x61]	31774	1			T2	187		T9	5		T10	9
valid_sources[0x62]	29915	1			T2	182		T9	2		T10	10
valid_sources[0x63]	37856	1			T2	133		T10	7		T58	5
valid_sources[0x64]	31423	1			T2	158		T3	561		T9	4
valid_sources[0x65]	30232	1			T2	200		T8	1		T9	3
valid_sources[0x66]	30576	1			T2	162		T10	5		T12	1
valid_sources[0x67]	31951	1			T2	150		T3	417		T9	4
valid_sources[0x68]	29035	1			T2	171		T6	2		T9	8
valid_sources[0x69]	29505	1			T2	132		T9	8		T10	12
valid_sources[0x6a]	32891	1			T2	147		T3	277		T9	7
valid_sources[0x6b]	31975	1			T2	148		T9	6		T10	9
valid_sources[0x6c]	35101	1			T1	15		T2	152		T9	1
valid_sources[0x6d]	32476	1			T2	238		T9	2		T10	4
valid_sources[0x6e]	30798	1			T2	200		T6	1		T9	1
valid_sources[0x6f]	43249	1			T2	160		T9	2		T10	12
valid_sources[0x70]	31421	1			T2	245		T3	4		T4	79
valid_sources[0x71]	31850	1			T2	143		T9	6		T10	9
valid_sources[0x72]	28245	1			T2	141		T3	1		T9	3
valid_sources[0x73]	29915	1			T2	161		T3	12		T9	1
valid_sources[0x74]	31499	1			T2	149		T9	3		T10	13
valid_sources[0x75]	32155	1			T2	103		T6	1		T9	3
valid_sources[0x76]	34013	1			T2	142		T9	1		T10	10
valid_sources[0x77]	28394	1			T2	106		T3	3		T9	5
valid_sources[0x78]	31252	1			T2	148		T9	1		T10	11
valid_sources[0x79]	28885	1			T2	172		T3	98		T9	4
valid_sources[0x7a]	32064	1			T2	137		T9	1		T10	11
valid_sources[0x7b]	33175	1			T2	187		T9	2		T10	4
valid_sources[0x7c]	29268	1			T2	194		T3	135		T9	3
valid_sources[0x7d]	29275	1			T2	156		T9	2		T10	15
valid_sources[0x7e]	45201	1			T2	160		T6	1		T7	7958
valid_sources[0x7f]	29079	1			T2	184		T3	4		T9	3
valid_sources[0x80]	29462	1			T2	192		T9	5		T10	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1118295

1

T2

1990

T3

981

T5

117

values[0x0]

all_enables

biggest_size

1628814

1

T1

3

T2

8993

T3

1333

values[0x1]

all_enables

biggest_size

1602348

1

T1

1

T2

8737

T3

1231