Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3836505

1

T1

11

T2

19595

T3

6668

full_word

4350753

1

T1

4

T2

19720

T3

3545

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8186898	1			T1	15		T2	39315		T3	10213
auto[TlIntgErrCmd]	129	1			T68	6		T100	3		T102	4
auto[TlIntgErrData]	113	1			T68	5		T100	3		T102	2
auto[TlIntgErrBoth]	118	1			T68	9		T100	4		T102	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4594639

1

T1

1

T2

19477

T3

6802

auto[1]

3592619

1

T1

14

T2

19838

T3

3411

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3475947	1			T1	1		T2	17487		T3	5821
auto[TlIntgErrNone]	partial	auto[1]	360231	1			T1	10		T2	2108		T3	847
auto[TlIntgErrNone]	full_word	auto[0]	1118545	1			T2	1990		T3	981		T5	117
auto[TlIntgErrNone]	full_word	auto[1]	3232175	1			T1	4		T2	17730		T3	2564
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T68	1		T100	2		T103	3
auto[TlIntgErrCmd]	partial	auto[1]	75	1			T68	5		T100	1		T102	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T102	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T178	1		T177	1		T179	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T68	1		T102	1		T103	5
auto[TlIntgErrData]	partial	auto[1]	58	1			T68	2		T100	2		T102	1
auto[TlIntgErrData]	full_word	auto[0]	9	1			T68	1		T103	1		T175	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T68	1		T100	1		T180	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T68	2		T100	2		T102	3
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T68	6		T100	2		T102	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T68	1		T116	1		T175	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T175	2		T158	1		T181	2