Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	612054244	3299489	0	0
gen_wmask[1].MaskCheckPortA_A	612054244	3299489	0	0
gen_wmask[2].MaskCheckPortA_A	612054244	3299489	0	0
gen_wmask[3].MaskCheckPortA_A	612054244	3299489	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612054244	3299489	0	0
T2	639646	14145	0	0
T3	658110	4369	0	0
T4	1119	0	0	0
T5	274010	837	0	0
T6	2413	0	0	0
T7	155138	832	0	0
T8	1551	0	0	0
T9	68586	832	0	0
T10	81750	832	0	0
T11	4114	38	0	0
T12	8602	836	0	0
T13	520	60	0	0
T15	0	9696	0	0
T16	0	4888	0	0
T29	0	1199	0	0
T44	0	4336	0	0
T58	0	832	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612054244	3299489	0	0
T2	639646	14145	0	0
T3	658110	4369	0	0
T4	1119	0	0	0
T5	274010	837	0	0
T6	2413	0	0	0
T7	155138	832	0	0
T8	1551	0	0	0
T9	68586	832	0	0
T10	81750	832	0	0
T11	4114	38	0	0
T12	8602	836	0	0
T13	520	60	0	0
T15	0	9696	0	0
T16	0	4888	0	0
T29	0	1199	0	0
T44	0	4336	0	0
T58	0	832	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612054244	3299489	0	0
T2	639646	14145	0	0
T3	658110	4369	0	0
T4	1119	0	0	0
T5	274010	837	0	0
T6	2413	0	0	0
T7	155138	832	0	0
T8	1551	0	0	0
T9	68586	832	0	0
T10	81750	832	0	0
T11	4114	38	0	0
T12	8602	836	0	0
T13	520	60	0	0
T15	0	9696	0	0
T16	0	4888	0	0
T29	0	1199	0	0
T44	0	4336	0	0
T58	0	832	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612054244	3299489	0	0
T2	639646	14145	0	0
T3	658110	4369	0	0
T4	1119	0	0	0
T5	274010	837	0	0
T6	2413	0	0	0
T7	155138	832	0	0
T8	1551	0	0	0
T9	68586	832	0	0
T10	81750	832	0	0
T11	4114	38	0	0
T12	8602	836	0	0
T13	520	60	0	0
T15	0	9696	0	0
T16	0	4888	0	0
T29	0	1199	0	0
T44	0	4336	0	0
T58	0	832	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T2,T3,T5

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	466340871	2074273	0	0
gen_wmask[1].MaskCheckPortA_A	466340871	2074273	0	0
gen_wmask[2].MaskCheckPortA_A	466340871	2074273	0	0
gen_wmask[3].MaskCheckPortA_A	466340871	2074273	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466340871	2074273	0	0
T2	147514	10393	0	0
T3	533213	1325	0	0
T4	1119	0	0	0
T5	241021	832	0	0
T6	1909	0	0	0
T7	119353	832	0	0
T8	1551	0	0	0
T9	59210	832	0	0
T10	58400	832	0	0
T11	3122	16	0	0
T12	0	832	0	0
T15	0	5959	0	0
T58	0	832	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466340871	2074273	0	0
T2	147514	10393	0	0
T3	533213	1325	0	0
T4	1119	0	0	0
T5	241021	832	0	0
T6	1909	0	0	0
T7	119353	832	0	0
T8	1551	0	0	0
T9	59210	832	0	0
T10	58400	832	0	0
T11	3122	16	0	0
T12	0	832	0	0
T15	0	5959	0	0
T58	0	832	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466340871	2074273	0	0
T2	147514	10393	0	0
T3	533213	1325	0	0
T4	1119	0	0	0
T5	241021	832	0	0
T6	1909	0	0	0
T7	119353	832	0	0
T8	1551	0	0	0
T9	59210	832	0	0
T10	58400	832	0	0
T11	3122	16	0	0
T12	0	832	0	0
T15	0	5959	0	0
T58	0	832	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466340871	2074273	0	0
T2	147514	10393	0	0
T3	533213	1325	0	0
T4	1119	0	0	0
T5	241021	832	0	0
T6	1909	0	0	0
T7	119353	832	0	0
T8	1551	0	0	0
T9	59210	832	0	0
T10	58400	832	0	0
T11	3122	16	0	0
T12	0	832	0	0
T15	0	5959	0	0
T58	0	832	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	145713373	1225216	0	0
gen_wmask[1].MaskCheckPortA_A	145713373	1225216	0	0
gen_wmask[2].MaskCheckPortA_A	145713373	1225216	0	0
gen_wmask[3].MaskCheckPortA_A	145713373	1225216	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	1225216	0	0
T2	492132	3752	0	0
T3	124897	3044	0	0
T5	32989	5	0	0
T6	504	0	0	0
T7	35785	0	0	0
T9	9376	0	0	0
T10	23350	0	0	0
T11	992	22	0	0
T12	8602	4	0	0
T13	520	60	0	0
T15	0	3737	0	0
T16	0	4888	0	0
T29	0	1199	0	0
T44	0	4336	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	1225216	0	0
T2	492132	3752	0	0
T3	124897	3044	0	0
T5	32989	5	0	0
T6	504	0	0	0
T7	35785	0	0	0
T9	9376	0	0	0
T10	23350	0	0	0
T11	992	22	0	0
T12	8602	4	0	0
T13	520	60	0	0
T15	0	3737	0	0
T16	0	4888	0	0
T29	0	1199	0	0
T44	0	4336	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	1225216	0	0
T2	492132	3752	0	0
T3	124897	3044	0	0
T5	32989	5	0	0
T6	504	0	0	0
T7	35785	0	0	0
T9	9376	0	0	0
T10	23350	0	0	0
T11	992	22	0	0
T12	8602	4	0	0
T13	520	60	0	0
T15	0	3737	0	0
T16	0	4888	0	0
T29	0	1199	0	0
T44	0	4336	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	1225216	0	0
T2	492132	3752	0	0
T3	124897	3044	0	0
T5	32989	5	0	0
T6	504	0	0	0
T7	35785	0	0	0
T9	9376	0	0	0
T10	23350	0	0	0
T11	992	22	0	0
T12	8602	4	0	0
T13	520	60	0	0
T15	0	3737	0	0
T16	0	4888	0	0
T29	0	1199	0	0
T44	0	4336	0	0