Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	468509944	2860466	0	0
DepthKnown_A	468509944	468384255	0	0
RvalidKnown_A	468509944	468384255	0	0
WreadyKnown_A	468509944	468384255	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	2860466	0	0
T2	147514	12476	0	0
T3	533213	0	0	0
T4	1119	0	0	0
T5	241021	832	0	0
T6	1909	0	0	0
T7	119353	832	0	0
T8	1551	0	0	0
T9	59210	1663	0	0
T10	58400	1663	0	0
T11	3122	0	0	0
T12	0	832	0	0
T15	0	6654	0	0
T16	0	14989	0	0
T17	0	1663	0	0
T58	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	468384255	0	0
T1	970	889	0	0
T2	147514	147508	0	0
T3	533213	533117	0	0
T4	1119	1059	0	0
T5	241021	240926	0	0
T6	1909	1814	0	0
T7	119353	119292	0	0
T8	1551	1461	0	0
T9	59210	59143	0	0
T10	58400	58306	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	468384255	0	0
T1	970	889	0	0
T2	147514	147508	0	0
T3	533213	533117	0	0
T4	1119	1059	0	0
T5	241021	240926	0	0
T6	1909	1814	0	0
T7	119353	119292	0	0
T8	1551	1461	0	0
T9	59210	59143	0	0
T10	58400	58306	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	468384255	0	0
T1	970	889	0	0
T2	147514	147508	0	0
T3	533213	533117	0	0
T4	1119	1059	0	0
T5	241021	240926	0	0
T6	1909	1814	0	0
T7	119353	119292	0	0
T8	1551	1461	0	0
T9	59210	59143	0	0
T10	58400	58306	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	468509944	3237943	0	0
DepthKnown_A	468509944	468384255	0	0
RvalidKnown_A	468509944	468384255	0	0
WreadyKnown_A	468509944	468384255	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	3237943	0	0
T2	147514	9152	0	0
T3	533213	0	0	0
T4	1119	0	0	0
T5	241021	832	0	0
T6	1909	0	0	0
T7	119353	832	0	0
T8	1551	0	0	0
T9	59210	832	0	0
T10	58400	832	0	0
T11	3122	0	0	0
T12	0	3692	0	0
T15	0	4992	0	0
T16	0	35044	0	0
T17	0	832	0	0
T58	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	468384255	0	0
T1	970	889	0	0
T2	147514	147508	0	0
T3	533213	533117	0	0
T4	1119	1059	0	0
T5	241021	240926	0	0
T6	1909	1814	0	0
T7	119353	119292	0	0
T8	1551	1461	0	0
T9	59210	59143	0	0
T10	58400	58306	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	468384255	0	0
T1	970	889	0	0
T2	147514	147508	0	0
T3	533213	533117	0	0
T4	1119	1059	0	0
T5	241021	240926	0	0
T6	1909	1814	0	0
T7	119353	119292	0	0
T8	1551	1461	0	0
T9	59210	59143	0	0
T10	58400	58306	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	468384255	0	0
T1	970	889	0	0
T2	147514	147508	0	0
T3	533213	533117	0	0
T4	1119	1059	0	0
T5	241021	240926	0	0
T6	1909	1814	0	0
T7	119353	119292	0	0
T8	1551	1461	0	0
T9	59210	59143	0	0
T10	58400	58306	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	468509944	190260	0	0
DepthKnown_A	468509944	468384255	0	0
RvalidKnown_A	468509944	468384255	0	0
WreadyKnown_A	468509944	468384255	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	190260	0	0
T2	147514	744	0	0
T3	533213	790	0	0
T4	1119	0	0	0
T5	241021	0	0	0
T6	1909	0	0	0
T7	119353	0	0	0
T8	1551	0	0	0
T9	59210	0	0	0
T10	58400	0	0	0
T11	3122	6	0	0
T13	0	15	0	0
T15	0	890	0	0
T16	0	624	0	0
T29	0	306	0	0
T44	0	922	0	0
T45	0	123	0	0
T46	0	1494	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	468384255	0	0
T1	970	889	0	0
T2	147514	147508	0	0
T3	533213	533117	0	0
T4	1119	1059	0	0
T5	241021	240926	0	0
T6	1909	1814	0	0
T7	119353	119292	0	0
T8	1551	1461	0	0
T9	59210	59143	0	0
T10	58400	58306	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	468384255	0	0
T1	970	889	0	0
T2	147514	147508	0	0
T3	533213	533117	0	0
T4	1119	1059	0	0
T5	241021	240926	0	0
T6	1909	1814	0	0
T7	119353	119292	0	0
T8	1551	1461	0	0
T9	59210	59143	0	0
T10	58400	58306	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	468384255	0	0
T1	970	889	0	0
T2	147514	147508	0	0
T3	533213	533117	0	0
T4	1119	1059	0	0
T5	241021	240926	0	0
T6	1909	1814	0	0
T7	119353	119292	0	0
T8	1551	1461	0	0
T9	59210	59143	0	0
T10	58400	58306	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	468509944	443123	0	0
DepthKnown_A	468509944	468384255	0	0
RvalidKnown_A	468509944	468384255	0	0
WreadyKnown_A	468509944	468384255	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	443123	0	0
T2	147514	744	0	0
T3	533213	3475	0	0
T4	1119	0	0	0
T5	241021	0	0	0
T6	1909	0	0	0
T7	119353	0	0	0
T8	1551	0	0	0
T9	59210	0	0	0
T10	58400	0	0	0
T11	3122	16	0	0
T13	0	61	0	0
T15	0	890	0	0
T16	0	2868	0	0
T29	0	306	0	0
T44	0	1769	0	0
T45	0	362	0	0
T46	0	6950	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	468384255	0	0
T1	970	889	0	0
T2	147514	147508	0	0
T3	533213	533117	0	0
T4	1119	1059	0	0
T5	241021	240926	0	0
T6	1909	1814	0	0
T7	119353	119292	0	0
T8	1551	1461	0	0
T9	59210	59143	0	0
T10	58400	58306	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	468384255	0	0
T1	970	889	0	0
T2	147514	147508	0	0
T3	533213	533117	0	0
T4	1119	1059	0	0
T5	241021	240926	0	0
T6	1909	1814	0	0
T7	119353	119292	0	0
T8	1551	1461	0	0
T9	59210	59143	0	0
T10	58400	58306	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	468384255	0	0
T1	970	889	0	0
T2	147514	147508	0	0
T3	533213	533117	0	0
T4	1119	1059	0	0
T5	241021	240926	0	0
T6	1909	1814	0	0
T7	119353	119292	0	0
T8	1551	1461	0	0
T9	59210	59143	0	0
T10	58400	58306	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	468509944	6528811	0	0
DepthKnown_A	468509944	468384255	0	0
RvalidKnown_A	468509944	468384255	0	0
WreadyKnown_A	468509944	468384255	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	6528811	0	0
T1	970	15	0	0
T2	147514	29618	0	0
T3	533213	9903	0	0
T4	1119	79	0	0
T5	241021	301	0	0
T6	1909	22	0	0
T7	119353	7126	0	0
T8	1551	11	0	0
T9	59210	46	0	0
T10	58400	1641	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	468384255	0	0
T1	970	889	0	0
T2	147514	147508	0	0
T3	533213	533117	0	0
T4	1119	1059	0	0
T5	241021	240926	0	0
T6	1909	1814	0	0
T7	119353	119292	0	0
T8	1551	1461	0	0
T9	59210	59143	0	0
T10	58400	58306	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	468384255	0	0
T1	970	889	0	0
T2	147514	147508	0	0
T3	533213	533117	0	0
T4	1119	1059	0	0
T5	241021	240926	0	0
T6	1909	1814	0	0
T7	119353	119292	0	0
T8	1551	1461	0	0
T9	59210	59143	0	0
T10	58400	58306	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	468384255	0	0
T1	970	889	0	0
T2	147514	147508	0	0
T3	533213	533117	0	0
T4	1119	1059	0	0
T5	241021	240926	0	0
T6	1909	1814	0	0
T7	119353	119292	0	0
T8	1551	1461	0	0
T9	59210	59143	0	0
T10	58400	58306	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	468509944	13925792	0	0
DepthKnown_A	468509944	468384255	0	0
RvalidKnown_A	468509944	468384255	0	0
WreadyKnown_A	468509944	468384255	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	13925792	0	0
T1	970	60	0	0
T2	147514	29419	0	0
T3	533213	41775	0	0
T4	1119	79	0	0
T5	241021	301	0	0
T6	1909	22	0	0
T7	119353	7126	0	0
T8	1551	11	0	0
T9	59210	46	0	0
T10	58400	1641	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	468384255	0	0
T1	970	889	0	0
T2	147514	147508	0	0
T3	533213	533117	0	0
T4	1119	1059	0	0
T5	241021	240926	0	0
T6	1909	1814	0	0
T7	119353	119292	0	0
T8	1551	1461	0	0
T9	59210	59143	0	0
T10	58400	58306	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	468384255	0	0
T1	970	889	0	0
T2	147514	147508	0	0
T3	533213	533117	0	0
T4	1119	1059	0	0
T5	241021	240926	0	0
T6	1909	1814	0	0
T7	119353	119292	0	0
T8	1551	1461	0	0
T9	59210	59143	0	0
T10	58400	58306	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468509944	468384255	0	0
T1	970	889	0	0
T2	147514	147508	0	0
T3	533213	533117	0	0
T4	1119	1059	0	0
T5	241021	240926	0	0
T6	1909	1814	0	0
T7	119353	119292	0	0
T8	1551	1461	0	0
T9	59210	59143	0	0
T10	58400	58306	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0