Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T11
1	0	Covered	T2,T3,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Unreachable
1	1	Covered	T2,T3,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T12
1	0	Covered	T2,T5,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T7
1	0	Unreachable
1	1	Covered	T2,T5,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	757767617	610616222	0	0
CheckNGreaterZero_A	2862	2862	0	0
GntImpliesReady_A	757767617	3696918	0	0
GntImpliesValid_A	757767617	3696918	0	0
GrantKnown_A	757767617	610616222	0	0
IdxKnown_A	757767617	610616222	0	0
IndexIsCorrect_A	757767617	3696918	0	0
LockArbDecision_A	757767617	0	0	0
NoReadyValidNoGrant_A	757767617	0	0	0
ReadyAndValidImplyGrant_A	757767617	3696918	0	0
ReqAndReadyImplyGrant_A	757767617	3696918	0	0
ReqImpliesValid_A	757767617	3696918	0	0
ReqStaysHighUntilGranted0_M	757767617	0	0	0
RoundRobin_A	757767617	7	0	954
ValidKnown_A	757767617	610616222	0	0
gen_data_port_assertion.DataFlow_A	757767617	3696918	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757767617	610616222	0	0
T1	970	889	0	0
T2	1131778	633159	0	0
T3	783007	653861	0	0
T4	1119	1059	0	0
T5	306999	273915	0	0
T6	2917	2318	0	0
T7	190923	153972	0	0
T8	1551	1461	0	0
T9	77962	68519	0	0
T10	105100	80670	0	0
T11	1984	992	0	0
T12	17204	8602	0	0
T13	1040	520	0	0
T15	0	453677	0	0
T16	0	809524	0	0
T17	0	22120	0	0
T18	0	8318	0	0
T27	0	720	0	0
T28	0	15576	0	0
T29	0	36720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2862	2862	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757767617	3696918	0	0
T2	1131778	16272	0	0
T3	783007	6629	0	0
T4	1119	0	0	0
T5	306999	841	0	0
T6	2917	0	0	0
T7	190923	832	0	0
T8	1551	0	0	0
T9	77962	832	0	0
T10	105100	832	0	0
T11	5106	61	0	0
T12	17204	840	0	0
T13	1040	75	0	0
T15	0	4791	0	0
T16	0	6193	0	0
T29	0	1692	0	0
T42	0	3010	0	0
T44	0	5004	0	0
T45	0	3381	0	0
T46	0	14900	0	0
T52	0	2726	0	0
T58	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757767617	3696918	0	0
T2	1131778	16272	0	0
T3	783007	6629	0	0
T4	1119	0	0	0
T5	306999	841	0	0
T6	2917	0	0	0
T7	190923	832	0	0
T8	1551	0	0	0
T9	77962	832	0	0
T10	105100	832	0	0
T11	5106	61	0	0
T12	17204	840	0	0
T13	1040	75	0	0
T15	0	4791	0	0
T16	0	6193	0	0
T29	0	1692	0	0
T42	0	3010	0	0
T44	0	5004	0	0
T45	0	3381	0	0
T46	0	14900	0	0
T52	0	2726	0	0
T58	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757767617	610616222	0	0
T1	970	889	0	0
T2	1131778	633159	0	0
T3	783007	653861	0	0
T4	1119	1059	0	0
T5	306999	273915	0	0
T6	2917	2318	0	0
T7	190923	153972	0	0
T8	1551	1461	0	0
T9	77962	68519	0	0
T10	105100	80670	0	0
T11	1984	992	0	0
T12	17204	8602	0	0
T13	1040	520	0	0
T15	0	453677	0	0
T16	0	809524	0	0
T17	0	22120	0	0
T18	0	8318	0	0
T27	0	720	0	0
T28	0	15576	0	0
T29	0	36720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757767617	610616222	0	0
T1	970	889	0	0
T2	1131778	633159	0	0
T3	783007	653861	0	0
T4	1119	1059	0	0
T5	306999	273915	0	0
T6	2917	2318	0	0
T7	190923	153972	0	0
T8	1551	1461	0	0
T9	77962	68519	0	0
T10	105100	80670	0	0
T11	1984	992	0	0
T12	17204	8602	0	0
T13	1040	520	0	0
T15	0	453677	0	0
T16	0	809524	0	0
T17	0	22120	0	0
T18	0	8318	0	0
T27	0	720	0	0
T28	0	15576	0	0
T29	0	36720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757767617	3696918	0	0
T2	1131778	16272	0	0
T3	783007	6629	0	0
T4	1119	0	0	0
T5	306999	841	0	0
T6	2917	0	0	0
T7	190923	832	0	0
T8	1551	0	0	0
T9	77962	832	0	0
T10	105100	832	0	0
T11	5106	61	0	0
T12	17204	840	0	0
T13	1040	75	0	0
T15	0	4791	0	0
T16	0	6193	0	0
T29	0	1692	0	0
T42	0	3010	0	0
T44	0	5004	0	0
T45	0	3381	0	0
T46	0	14900	0	0
T52	0	2726	0	0
T58	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757767617	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757767617	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757767617	3696918	0	0
T2	1131778	16272	0	0
T3	783007	6629	0	0
T4	1119	0	0	0
T5	306999	841	0	0
T6	2917	0	0	0
T7	190923	832	0	0
T8	1551	0	0	0
T9	77962	832	0	0
T10	105100	832	0	0
T11	5106	61	0	0
T12	17204	840	0	0
T13	1040	75	0	0
T15	0	4791	0	0
T16	0	6193	0	0
T29	0	1692	0	0
T42	0	3010	0	0
T44	0	5004	0	0
T45	0	3381	0	0
T46	0	14900	0	0
T52	0	2726	0	0
T58	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757767617	3696918	0	0
T2	1131778	16272	0	0
T3	783007	6629	0	0
T4	1119	0	0	0
T5	306999	841	0	0
T6	2917	0	0	0
T7	190923	832	0	0
T8	1551	0	0	0
T9	77962	832	0	0
T10	105100	832	0	0
T11	5106	61	0	0
T12	17204	840	0	0
T13	1040	75	0	0
T15	0	4791	0	0
T16	0	6193	0	0
T29	0	1692	0	0
T42	0	3010	0	0
T44	0	5004	0	0
T45	0	3381	0	0
T46	0	14900	0	0
T52	0	2726	0	0
T58	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757767617	3696918	0	0
T2	1131778	16272	0	0
T3	783007	6629	0	0
T4	1119	0	0	0
T5	306999	841	0	0
T6	2917	0	0	0
T7	190923	832	0	0
T8	1551	0	0	0
T9	77962	832	0	0
T10	105100	832	0	0
T11	5106	61	0	0
T12	17204	840	0	0
T13	1040	75	0	0
T15	0	4791	0	0
T16	0	6193	0	0
T29	0	1692	0	0
T42	0	3010	0	0
T44	0	5004	0	0
T45	0	3381	0	0
T46	0	14900	0	0
T52	0	2726	0	0
T58	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	757767617	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757767617	7	0	954
T19	171765	1	0	1
T20	115039	0	0	1
T24	58384	0	0	1
T25	11957	0	0	1
T26	572378	0	0	1
T36	180449	0	0	1
T37	24971	0	0	1
T38	1059	0	0	1
T39	11103	0	0	1
T40	200706	0	0	1
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757767617	610616222	0	0
T1	970	889	0	0
T2	1131778	633159	0	0
T3	783007	653861	0	0
T4	1119	1059	0	0
T5	306999	273915	0	0
T6	2917	2318	0	0
T7	190923	153972	0	0
T8	1551	1461	0	0
T9	77962	68519	0	0
T10	105100	80670	0	0
T11	1984	992	0	0
T12	17204	8602	0	0
T13	1040	520	0	0
T15	0	453677	0	0
T16	0	809524	0	0
T17	0	22120	0	0
T18	0	8318	0	0
T27	0	720	0	0
T28	0	15576	0	0
T29	0	36720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757767617	3696918	0	0
T2	1131778	16272	0	0
T3	783007	6629	0	0
T4	1119	0	0	0
T5	306999	841	0	0
T6	2917	0	0	0
T7	190923	832	0	0
T8	1551	0	0	0
T9	77962	832	0	0
T10	105100	832	0	0
T11	5106	61	0	0
T12	17204	840	0	0
T13	1040	75	0	0
T15	0	4791	0	0
T16	0	6193	0	0
T29	0	1692	0	0
T42	0	3010	0	0
T44	0	5004	0	0
T45	0	3381	0	0
T46	0	14900	0	0
T52	0	2726	0	0
T58	0	832	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T11
1	0	Covered	T2,T3,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Unreachable
1	1	Covered	T2,T3,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T11
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	145713373	27551210	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	145713373	648932	0	0
GntImpliesValid_A	145713373	648932	0	0
GrantKnown_A	145713373	27551210	0	0
IdxKnown_A	145713373	27551210	0	0
IndexIsCorrect_A	145713373	648932	0	0
LockArbDecision_A	145713373	0	0	0
NoReadyValidNoGrant_A	145713373	0	0	0
ReadyAndValidImplyGrant_A	145713373	648932	0	0
ReqAndReadyImplyGrant_A	145713373	648932	0	0
ReqImpliesValid_A	145713373	648932	0	0
ReqStaysHighUntilGranted0_M	145713373	0	0	0
RoundRobin_A	145713373	0	0	0
ValidKnown_A	145713373	27551210	0	0
gen_data_port_assertion.DataFlow_A	145713373	648932	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	27551210	0	0
T2	492132	96680	0	0
T3	124897	120744	0	0
T5	32989	0	0	0
T6	504	504	0	0
T7	35785	0	0	0
T9	9376	0	0	0
T10	23350	0	0	0
T11	992	992	0	0
T12	8602	0	0	0
T13	520	520	0	0
T15	0	79336	0	0
T16	0	79952	0	0
T27	0	720	0	0
T28	0	15576	0	0
T29	0	36720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	648932	0	0
T2	492132	3542	0	0
T3	124897	4514	0	0
T5	32989	0	0	0
T6	504	0	0	0
T7	35785	0	0	0
T9	9376	0	0	0
T10	23350	0	0	0
T11	992	39	0	0
T12	8602	0	0	0
T13	520	60	0	0
T15	0	3991	0	0
T16	0	2713	0	0
T29	0	1692	0	0
T44	0	1943	0	0
T45	0	391	0	0
T46	0	5966	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	648932	0	0
T2	492132	3542	0	0
T3	124897	4514	0	0
T5	32989	0	0	0
T6	504	0	0	0
T7	35785	0	0	0
T9	9376	0	0	0
T10	23350	0	0	0
T11	992	39	0	0
T12	8602	0	0	0
T13	520	60	0	0
T15	0	3991	0	0
T16	0	2713	0	0
T29	0	1692	0	0
T44	0	1943	0	0
T45	0	391	0	0
T46	0	5966	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	27551210	0	0
T2	492132	96680	0	0
T3	124897	120744	0	0
T5	32989	0	0	0
T6	504	504	0	0
T7	35785	0	0	0
T9	9376	0	0	0
T10	23350	0	0	0
T11	992	992	0	0
T12	8602	0	0	0
T13	520	520	0	0
T15	0	79336	0	0
T16	0	79952	0	0
T27	0	720	0	0
T28	0	15576	0	0
T29	0	36720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	27551210	0	0
T2	492132	96680	0	0
T3	124897	120744	0	0
T5	32989	0	0	0
T6	504	504	0	0
T7	35785	0	0	0
T9	9376	0	0	0
T10	23350	0	0	0
T11	992	992	0	0
T12	8602	0	0	0
T13	520	520	0	0
T15	0	79336	0	0
T16	0	79952	0	0
T27	0	720	0	0
T28	0	15576	0	0
T29	0	36720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	648932	0	0
T2	492132	3542	0	0
T3	124897	4514	0	0
T5	32989	0	0	0
T6	504	0	0	0
T7	35785	0	0	0
T9	9376	0	0	0
T10	23350	0	0	0
T11	992	39	0	0
T12	8602	0	0	0
T13	520	60	0	0
T15	0	3991	0	0
T16	0	2713	0	0
T29	0	1692	0	0
T44	0	1943	0	0
T45	0	391	0	0
T46	0	5966	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	648932	0	0
T2	492132	3542	0	0
T3	124897	4514	0	0
T5	32989	0	0	0
T6	504	0	0	0
T7	35785	0	0	0
T9	9376	0	0	0
T10	23350	0	0	0
T11	992	39	0	0
T12	8602	0	0	0
T13	520	60	0	0
T15	0	3991	0	0
T16	0	2713	0	0
T29	0	1692	0	0
T44	0	1943	0	0
T45	0	391	0	0
T46	0	5966	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	648932	0	0
T2	492132	3542	0	0
T3	124897	4514	0	0
T5	32989	0	0	0
T6	504	0	0	0
T7	35785	0	0	0
T9	9376	0	0	0
T10	23350	0	0	0
T11	992	39	0	0
T12	8602	0	0	0
T13	520	60	0	0
T15	0	3991	0	0
T16	0	2713	0	0
T29	0	1692	0	0
T44	0	1943	0	0
T45	0	391	0	0
T46	0	5966	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	648932	0	0
T2	492132	3542	0	0
T3	124897	4514	0	0
T5	32989	0	0	0
T6	504	0	0	0
T7	35785	0	0	0
T9	9376	0	0	0
T10	23350	0	0	0
T11	992	39	0	0
T12	8602	0	0	0
T13	520	60	0	0
T15	0	3991	0	0
T16	0	2713	0	0
T29	0	1692	0	0
T44	0	1943	0	0
T45	0	391	0	0
T46	0	5966	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	27551210	0	0
T2	492132	96680	0	0
T3	124897	120744	0	0
T5	32989	0	0	0
T6	504	504	0	0
T7	35785	0	0	0
T9	9376	0	0	0
T10	23350	0	0	0
T11	992	992	0	0
T12	8602	0	0	0
T13	520	520	0	0
T15	0	79336	0	0
T16	0	79952	0	0
T27	0	720	0	0
T28	0	15576	0	0
T29	0	36720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	648932	0	0
T2	492132	3542	0	0
T3	124897	4514	0	0
T5	32989	0	0	0
T6	504	0	0	0
T7	35785	0	0	0
T9	9376	0	0	0
T10	23350	0	0	0
T11	992	39	0	0
T12	8602	0	0	0
T13	520	60	0	0
T15	0	3991	0	0
T16	0	2713	0	0
T29	0	1692	0	0
T44	0	1943	0	0
T45	0	391	0	0
T46	0	5966	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T12
1	0	Covered	T2,T5,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T7
1	0	Unreachable
1	1	Covered	T2,T5,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T5,T12
0	0	1	Unreachable
0	0	0	Covered	T2,T5,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	145713373	116807775	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	145713373	791182	0	0
GntImpliesValid_A	145713373	791182	0	0
GrantKnown_A	145713373	116807775	0	0
IdxKnown_A	145713373	116807775	0	0
IndexIsCorrect_A	145713373	791182	0	0
LockArbDecision_A	145713373	0	0	0
NoReadyValidNoGrant_A	145713373	0	0	0
ReadyAndValidImplyGrant_A	145713373	791182	0	0
ReqAndReadyImplyGrant_A	145713373	791182	0	0
ReqImpliesValid_A	145713373	791182	0	0
ReqStaysHighUntilGranted0_M	145713373	0	0	0
RoundRobin_A	145713373	0	0	0
ValidKnown_A	145713373	116807775	0	0
gen_data_port_assertion.DataFlow_A	145713373	791182	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	116807775	0	0
T2	492132	388971	0	0
T3	124897	0	0	0
T5	32989	32989	0	0
T6	504	0	0	0
T7	35785	34680	0	0
T9	9376	9376	0	0
T10	23350	22364	0	0
T11	992	0	0	0
T12	8602	8602	0	0
T13	520	0	0	0
T15	0	374341	0	0
T16	0	729572	0	0
T17	0	22120	0	0
T18	0	8318	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	791182	0	0
T2	492132	1574	0	0
T3	124897	0	0	0
T5	32989	5	0	0
T6	504	0	0	0
T7	35785	0	0	0
T9	9376	0	0	0
T10	23350	0	0	0
T11	992	0	0	0
T12	8602	4	0	0
T13	520	0	0	0
T15	0	800	0	0
T16	0	3480	0	0
T42	0	3010	0	0
T44	0	3061	0	0
T45	0	2990	0	0
T46	0	8934	0	0
T52	0	2726	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	791182	0	0
T2	492132	1574	0	0
T3	124897	0	0	0
T5	32989	5	0	0
T6	504	0	0	0
T7	35785	0	0	0
T9	9376	0	0	0
T10	23350	0	0	0
T11	992	0	0	0
T12	8602	4	0	0
T13	520	0	0	0
T15	0	800	0	0
T16	0	3480	0	0
T42	0	3010	0	0
T44	0	3061	0	0
T45	0	2990	0	0
T46	0	8934	0	0
T52	0	2726	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	116807775	0	0
T2	492132	388971	0	0
T3	124897	0	0	0
T5	32989	32989	0	0
T6	504	0	0	0
T7	35785	34680	0	0
T9	9376	9376	0	0
T10	23350	22364	0	0
T11	992	0	0	0
T12	8602	8602	0	0
T13	520	0	0	0
T15	0	374341	0	0
T16	0	729572	0	0
T17	0	22120	0	0
T18	0	8318	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	116807775	0	0
T2	492132	388971	0	0
T3	124897	0	0	0
T5	32989	32989	0	0
T6	504	0	0	0
T7	35785	34680	0	0
T9	9376	9376	0	0
T10	23350	22364	0	0
T11	992	0	0	0
T12	8602	8602	0	0
T13	520	0	0	0
T15	0	374341	0	0
T16	0	729572	0	0
T17	0	22120	0	0
T18	0	8318	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	791182	0	0
T2	492132	1574	0	0
T3	124897	0	0	0
T5	32989	5	0	0
T6	504	0	0	0
T7	35785	0	0	0
T9	9376	0	0	0
T10	23350	0	0	0
T11	992	0	0	0
T12	8602	4	0	0
T13	520	0	0	0
T15	0	800	0	0
T16	0	3480	0	0
T42	0	3010	0	0
T44	0	3061	0	0
T45	0	2990	0	0
T46	0	8934	0	0
T52	0	2726	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	791182	0	0
T2	492132	1574	0	0
T3	124897	0	0	0
T5	32989	5	0	0
T6	504	0	0	0
T7	35785	0	0	0
T9	9376	0	0	0
T10	23350	0	0	0
T11	992	0	0	0
T12	8602	4	0	0
T13	520	0	0	0
T15	0	800	0	0
T16	0	3480	0	0
T42	0	3010	0	0
T44	0	3061	0	0
T45	0	2990	0	0
T46	0	8934	0	0
T52	0	2726	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	791182	0	0
T2	492132	1574	0	0
T3	124897	0	0	0
T5	32989	5	0	0
T6	504	0	0	0
T7	35785	0	0	0
T9	9376	0	0	0
T10	23350	0	0	0
T11	992	0	0	0
T12	8602	4	0	0
T13	520	0	0	0
T15	0	800	0	0
T16	0	3480	0	0
T42	0	3010	0	0
T44	0	3061	0	0
T45	0	2990	0	0
T46	0	8934	0	0
T52	0	2726	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	791182	0	0
T2	492132	1574	0	0
T3	124897	0	0	0
T5	32989	5	0	0
T6	504	0	0	0
T7	35785	0	0	0
T9	9376	0	0	0
T10	23350	0	0	0
T11	992	0	0	0
T12	8602	4	0	0
T13	520	0	0	0
T15	0	800	0	0
T16	0	3480	0	0
T42	0	3010	0	0
T44	0	3061	0	0
T45	0	2990	0	0
T46	0	8934	0	0
T52	0	2726	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	116807775	0	0
T2	492132	388971	0	0
T3	124897	0	0	0
T5	32989	32989	0	0
T6	504	0	0	0
T7	35785	34680	0	0
T9	9376	9376	0	0
T10	23350	22364	0	0
T11	992	0	0	0
T12	8602	8602	0	0
T13	520	0	0	0
T15	0	374341	0	0
T16	0	729572	0	0
T17	0	22120	0	0
T18	0	8318	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145713373	791182	0	0
T2	492132	1574	0	0
T3	124897	0	0	0
T5	32989	5	0	0
T6	504	0	0	0
T7	35785	0	0	0
T9	9376	0	0	0
T10	23350	0	0	0
T11	992	0	0	0
T12	8602	4	0	0
T13	520	0	0	0
T15	0	800	0	0
T16	0	3480	0	0
T42	0	3010	0	0
T44	0	3061	0	0
T45	0	2990	0	0
T46	0	8934	0	0
T52	0	2726	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	466340871	466257237	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	466340871	2256804	0	0
GntImpliesValid_A	466340871	2256804	0	0
GrantKnown_A	466340871	466257237	0	0
IdxKnown_A	466340871	466257237	0	0
IndexIsCorrect_A	466340871	2256804	0	0
LockArbDecision_A	466340871	0	0	0
NoReadyValidNoGrant_A	466340871	0	0	0
ReadyAndValidImplyGrant_A	466340871	2256804	0	0
ReqAndReadyImplyGrant_A	466340871	2256804	0	0
ReqImpliesValid_A	466340871	2256804	0	0
ReqStaysHighUntilGranted0_M	466340871	0	0	0
RoundRobin_A	466340871	7	0	954
ValidKnown_A	466340871	466257237	0	0
gen_data_port_assertion.DataFlow_A	466340871	2256804	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466340871	466257237	0	0
T1	970	889	0	0
T2	147514	147508	0	0
T3	533213	533117	0	0
T4	1119	1059	0	0
T5	241021	240926	0	0
T6	1909	1814	0	0
T7	119353	119292	0	0
T8	1551	1461	0	0
T9	59210	59143	0	0
T10	58400	58306	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466340871	2256804	0	0
T2	147514	11156	0	0
T3	533213	2115	0	0
T4	1119	0	0	0
T5	241021	836	0	0
T6	1909	0	0	0
T7	119353	832	0	0
T8	1551	0	0	0
T9	59210	832	0	0
T10	58400	832	0	0
T11	3122	22	0	0
T12	0	836	0	0
T13	0	15	0	0
T58	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466340871	2256804	0	0
T2	147514	11156	0	0
T3	533213	2115	0	0
T4	1119	0	0	0
T5	241021	836	0	0
T6	1909	0	0	0
T7	119353	832	0	0
T8	1551	0	0	0
T9	59210	832	0	0
T10	58400	832	0	0
T11	3122	22	0	0
T12	0	836	0	0
T13	0	15	0	0
T58	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466340871	466257237	0	0
T1	970	889	0	0
T2	147514	147508	0	0
T3	533213	533117	0	0
T4	1119	1059	0	0
T5	241021	240926	0	0
T6	1909	1814	0	0
T7	119353	119292	0	0
T8	1551	1461	0	0
T9	59210	59143	0	0
T10	58400	58306	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466340871	466257237	0	0
T1	970	889	0	0
T2	147514	147508	0	0
T3	533213	533117	0	0
T4	1119	1059	0	0
T5	241021	240926	0	0
T6	1909	1814	0	0
T7	119353	119292	0	0
T8	1551	1461	0	0
T9	59210	59143	0	0
T10	58400	58306	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466340871	2256804	0	0
T2	147514	11156	0	0
T3	533213	2115	0	0
T4	1119	0	0	0
T5	241021	836	0	0
T6	1909	0	0	0
T7	119353	832	0	0
T8	1551	0	0	0
T9	59210	832	0	0
T10	58400	832	0	0
T11	3122	22	0	0
T12	0	836	0	0
T13	0	15	0	0
T58	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466340871	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466340871	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466340871	2256804	0	0
T2	147514	11156	0	0
T3	533213	2115	0	0
T4	1119	0	0	0
T5	241021	836	0	0
T6	1909	0	0	0
T7	119353	832	0	0
T8	1551	0	0	0
T9	59210	832	0	0
T10	58400	832	0	0
T11	3122	22	0	0
T12	0	836	0	0
T13	0	15	0	0
T58	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466340871	2256804	0	0
T2	147514	11156	0	0
T3	533213	2115	0	0
T4	1119	0	0	0
T5	241021	836	0	0
T6	1909	0	0	0
T7	119353	832	0	0
T8	1551	0	0	0
T9	59210	832	0	0
T10	58400	832	0	0
T11	3122	22	0	0
T12	0	836	0	0
T13	0	15	0	0
T58	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466340871	2256804	0	0
T2	147514	11156	0	0
T3	533213	2115	0	0
T4	1119	0	0	0
T5	241021	836	0	0
T6	1909	0	0	0
T7	119353	832	0	0
T8	1551	0	0	0
T9	59210	832	0	0
T10	58400	832	0	0
T11	3122	22	0	0
T12	0	836	0	0
T13	0	15	0	0
T58	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	466340871	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466340871	7	0	954
T19	171765	1	0	1
T20	115039	0	0	1
T24	58384	0	0	1
T25	11957	0	0	1
T26	572378	0	0	1
T36	180449	0	0	1
T37	24971	0	0	1
T38	1059	0	0	1
T39	11103	0	0	1
T40	200706	0	0	1
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466340871	466257237	0	0
T1	970	889	0	0
T2	147514	147508	0	0
T3	533213	533117	0	0
T4	1119	1059	0	0
T5	241021	240926	0	0
T6	1909	1814	0	0
T7	119353	119292	0	0
T8	1551	1461	0	0
T9	59210	59143	0	0
T10	58400	58306	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466340871	2256804	0	0
T2	147514	11156	0	0
T3	533213	2115	0	0
T4	1119	0	0	0
T5	241021	836	0	0
T6	1909	0	0	0
T7	119353	832	0	0
T8	1551	0	0	0
T9	59210	832	0	0
T10	58400	832	0	0
T11	3122	22	0	0
T12	0	836	0	0
T13	0	15	0	0
T58	0	832	0	0