Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
3760 |
0 |
0 |
T68 |
51522 |
2 |
0 |
0 |
T69 |
3027 |
55 |
0 |
0 |
T99 |
12296 |
4 |
0 |
0 |
T101 |
2556 |
2 |
0 |
0 |
T102 |
10319 |
1 |
0 |
0 |
T103 |
55932 |
2 |
0 |
0 |
T104 |
18868 |
258 |
0 |
0 |
T105 |
4643 |
165 |
0 |
0 |
T112 |
2470 |
4 |
0 |
0 |
T116 |
34551 |
1 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
1715 |
0 |
0 |
T116 |
34551 |
29 |
0 |
0 |
T119 |
7721 |
12 |
0 |
0 |
T127 |
90642 |
227 |
0 |
0 |
T143 |
14579 |
70 |
0 |
0 |
T153 |
14139 |
52 |
0 |
0 |
T154 |
13594 |
86 |
0 |
0 |
T155 |
20573 |
15 |
0 |
0 |
T156 |
8985 |
7 |
0 |
0 |
T157 |
7876 |
14 |
0 |
0 |
T158 |
102367 |
115 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
1765 |
0 |
0 |
T116 |
34551 |
54 |
0 |
0 |
T119 |
7721 |
4 |
0 |
0 |
T127 |
90642 |
267 |
0 |
0 |
T143 |
14579 |
54 |
0 |
0 |
T153 |
14139 |
39 |
0 |
0 |
T154 |
13594 |
80 |
0 |
0 |
T155 |
20573 |
67 |
0 |
0 |
T156 |
8985 |
9 |
0 |
0 |
T157 |
7876 |
30 |
0 |
0 |
T158 |
102367 |
108 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
1968 |
0 |
0 |
T104 |
18868 |
1 |
0 |
0 |
T116 |
34551 |
44 |
0 |
0 |
T119 |
7721 |
20 |
0 |
0 |
T127 |
90642 |
207 |
0 |
0 |
T143 |
14579 |
91 |
0 |
0 |
T153 |
14139 |
37 |
0 |
0 |
T154 |
13594 |
22 |
0 |
0 |
T155 |
20573 |
60 |
0 |
0 |
T156 |
8985 |
5 |
0 |
0 |
T157 |
7876 |
26 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
8050 |
0 |
0 |
T116 |
34551 |
254 |
0 |
0 |
T119 |
7721 |
117 |
0 |
0 |
T127 |
90642 |
247 |
0 |
0 |
T143 |
14579 |
47 |
0 |
0 |
T153 |
14139 |
50 |
0 |
0 |
T154 |
13594 |
78 |
0 |
0 |
T155 |
20573 |
70 |
0 |
0 |
T156 |
8985 |
8 |
0 |
0 |
T157 |
7876 |
43 |
0 |
0 |
T158 |
102367 |
1169 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
8069 |
0 |
0 |
T116 |
34551 |
521 |
0 |
0 |
T119 |
7721 |
236 |
0 |
0 |
T127 |
90642 |
232 |
0 |
0 |
T143 |
14579 |
45 |
0 |
0 |
T153 |
14139 |
17 |
0 |
0 |
T154 |
13594 |
22 |
0 |
0 |
T155 |
20573 |
46 |
0 |
0 |
T156 |
8985 |
117 |
0 |
0 |
T157 |
7876 |
15 |
0 |
0 |
T158 |
102367 |
1664 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
8796 |
0 |
0 |
T116 |
34551 |
731 |
0 |
0 |
T119 |
7721 |
125 |
0 |
0 |
T127 |
90642 |
229 |
0 |
0 |
T143 |
14579 |
39 |
0 |
0 |
T153 |
14139 |
93 |
0 |
0 |
T154 |
13594 |
49 |
0 |
0 |
T155 |
20573 |
88 |
0 |
0 |
T156 |
8985 |
218 |
0 |
0 |
T157 |
7876 |
7 |
0 |
0 |
T158 |
102367 |
1595 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
7676 |
0 |
0 |
T116 |
34551 |
580 |
0 |
0 |
T119 |
7721 |
97 |
0 |
0 |
T127 |
90642 |
213 |
0 |
0 |
T143 |
14579 |
15 |
0 |
0 |
T153 |
14139 |
68 |
0 |
0 |
T154 |
13594 |
90 |
0 |
0 |
T155 |
20573 |
71 |
0 |
0 |
T156 |
8985 |
15 |
0 |
0 |
T157 |
7876 |
28 |
0 |
0 |
T158 |
102367 |
1645 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
7558 |
0 |
0 |
T104 |
18868 |
5 |
0 |
0 |
T116 |
34551 |
310 |
0 |
0 |
T119 |
7721 |
149 |
0 |
0 |
T127 |
90642 |
181 |
0 |
0 |
T143 |
14579 |
60 |
0 |
0 |
T153 |
14139 |
36 |
0 |
0 |
T154 |
13594 |
25 |
0 |
0 |
T155 |
20573 |
56 |
0 |
0 |
T156 |
8985 |
258 |
0 |
0 |
T158 |
102367 |
1345 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
8477 |
0 |
0 |
T116 |
34551 |
532 |
0 |
0 |
T119 |
7721 |
213 |
0 |
0 |
T127 |
90642 |
240 |
0 |
0 |
T143 |
14579 |
13 |
0 |
0 |
T153 |
14139 |
61 |
0 |
0 |
T154 |
13594 |
34 |
0 |
0 |
T155 |
20573 |
50 |
0 |
0 |
T156 |
8985 |
11 |
0 |
0 |
T157 |
7876 |
12 |
0 |
0 |
T158 |
102367 |
2398 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
8281 |
0 |
0 |
T116 |
34551 |
490 |
0 |
0 |
T119 |
7721 |
93 |
0 |
0 |
T127 |
90642 |
210 |
0 |
0 |
T143 |
14579 |
55 |
0 |
0 |
T153 |
14139 |
65 |
0 |
0 |
T154 |
13594 |
50 |
0 |
0 |
T155 |
20573 |
27 |
0 |
0 |
T156 |
8985 |
222 |
0 |
0 |
T157 |
7876 |
17 |
0 |
0 |
T158 |
102367 |
1541 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
8326 |
0 |
0 |
T116 |
34551 |
605 |
0 |
0 |
T119 |
7721 |
124 |
0 |
0 |
T127 |
90642 |
232 |
0 |
0 |
T143 |
14579 |
49 |
0 |
0 |
T153 |
14139 |
38 |
0 |
0 |
T154 |
13594 |
5 |
0 |
0 |
T155 |
20573 |
47 |
0 |
0 |
T156 |
8985 |
129 |
0 |
0 |
T157 |
7876 |
17 |
0 |
0 |
T158 |
102367 |
1990 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
4177 |
0 |
0 |
T116 |
34551 |
419 |
0 |
0 |
T119 |
7721 |
91 |
0 |
0 |
T127 |
90642 |
274 |
0 |
0 |
T143 |
14579 |
12 |
0 |
0 |
T153 |
14139 |
38 |
0 |
0 |
T154 |
13594 |
62 |
0 |
0 |
T155 |
20573 |
25 |
0 |
0 |
T156 |
8985 |
18 |
0 |
0 |
T157 |
7876 |
37 |
0 |
0 |
T158 |
102367 |
724 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
4590 |
0 |
0 |
T116 |
34551 |
280 |
0 |
0 |
T119 |
7721 |
2 |
0 |
0 |
T127 |
90642 |
256 |
0 |
0 |
T143 |
14579 |
50 |
0 |
0 |
T153 |
14139 |
33 |
0 |
0 |
T154 |
13594 |
30 |
0 |
0 |
T155 |
20573 |
79 |
0 |
0 |
T156 |
8985 |
33 |
0 |
0 |
T157 |
7876 |
46 |
0 |
0 |
T158 |
102367 |
896 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
3922 |
0 |
0 |
T104 |
18868 |
4 |
0 |
0 |
T110 |
12140 |
4 |
0 |
0 |
T116 |
34551 |
262 |
0 |
0 |
T119 |
7721 |
49 |
0 |
0 |
T127 |
90642 |
197 |
0 |
0 |
T143 |
14579 |
33 |
0 |
0 |
T153 |
14139 |
68 |
0 |
0 |
T154 |
13594 |
28 |
0 |
0 |
T155 |
20573 |
51 |
0 |
0 |
T156 |
8985 |
50 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
4223 |
0 |
0 |
T116 |
34551 |
207 |
0 |
0 |
T119 |
7721 |
58 |
0 |
0 |
T127 |
90642 |
239 |
0 |
0 |
T143 |
14579 |
17 |
0 |
0 |
T153 |
14139 |
42 |
0 |
0 |
T154 |
13594 |
14 |
0 |
0 |
T155 |
20573 |
10 |
0 |
0 |
T156 |
8985 |
94 |
0 |
0 |
T157 |
7876 |
22 |
0 |
0 |
T158 |
102367 |
769 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
4120 |
0 |
0 |
T116 |
34551 |
324 |
0 |
0 |
T119 |
7721 |
14 |
0 |
0 |
T127 |
90642 |
224 |
0 |
0 |
T143 |
14579 |
22 |
0 |
0 |
T153 |
14139 |
87 |
0 |
0 |
T154 |
13594 |
10 |
0 |
0 |
T155 |
20573 |
54 |
0 |
0 |
T156 |
8985 |
67 |
0 |
0 |
T157 |
7876 |
44 |
0 |
0 |
T158 |
102367 |
698 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
4168 |
0 |
0 |
T116 |
34551 |
157 |
0 |
0 |
T119 |
7721 |
113 |
0 |
0 |
T127 |
90642 |
234 |
0 |
0 |
T143 |
14579 |
43 |
0 |
0 |
T153 |
14139 |
80 |
0 |
0 |
T154 |
13594 |
37 |
0 |
0 |
T155 |
20573 |
44 |
0 |
0 |
T156 |
8985 |
116 |
0 |
0 |
T157 |
7876 |
12 |
0 |
0 |
T158 |
102367 |
771 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
4609 |
0 |
0 |
T116 |
34551 |
265 |
0 |
0 |
T119 |
7721 |
44 |
0 |
0 |
T127 |
90642 |
228 |
0 |
0 |
T143 |
14579 |
33 |
0 |
0 |
T153 |
14139 |
74 |
0 |
0 |
T154 |
13594 |
45 |
0 |
0 |
T155 |
20573 |
32 |
0 |
0 |
T156 |
8985 |
50 |
0 |
0 |
T157 |
7876 |
6 |
0 |
0 |
T158 |
102367 |
852 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
4245 |
0 |
0 |
T116 |
34551 |
108 |
0 |
0 |
T124 |
10522 |
39 |
0 |
0 |
T127 |
90642 |
189 |
0 |
0 |
T143 |
14579 |
17 |
0 |
0 |
T153 |
14139 |
52 |
0 |
0 |
T154 |
13594 |
55 |
0 |
0 |
T155 |
20573 |
113 |
0 |
0 |
T156 |
8985 |
67 |
0 |
0 |
T157 |
7876 |
7 |
0 |
0 |
T158 |
102367 |
560 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
4106 |
0 |
0 |
T116 |
34551 |
205 |
0 |
0 |
T119 |
7721 |
4 |
0 |
0 |
T127 |
90642 |
293 |
0 |
0 |
T143 |
14579 |
44 |
0 |
0 |
T153 |
14139 |
50 |
0 |
0 |
T154 |
13594 |
13 |
0 |
0 |
T155 |
20573 |
63 |
0 |
0 |
T156 |
8985 |
2 |
0 |
0 |
T157 |
7876 |
18 |
0 |
0 |
T158 |
102367 |
756 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
4639 |
0 |
0 |
T116 |
34551 |
242 |
0 |
0 |
T119 |
7721 |
77 |
0 |
0 |
T127 |
90642 |
232 |
0 |
0 |
T143 |
14579 |
74 |
0 |
0 |
T153 |
14139 |
51 |
0 |
0 |
T154 |
13594 |
58 |
0 |
0 |
T155 |
20573 |
78 |
0 |
0 |
T156 |
8985 |
12 |
0 |
0 |
T157 |
7876 |
28 |
0 |
0 |
T158 |
102367 |
1041 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
4304 |
0 |
0 |
T116 |
34551 |
347 |
0 |
0 |
T119 |
7721 |
64 |
0 |
0 |
T127 |
90642 |
215 |
0 |
0 |
T143 |
14579 |
40 |
0 |
0 |
T153 |
14139 |
51 |
0 |
0 |
T154 |
13594 |
29 |
0 |
0 |
T155 |
20573 |
78 |
0 |
0 |
T156 |
8985 |
100 |
0 |
0 |
T157 |
7876 |
3 |
0 |
0 |
T158 |
102367 |
911 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
4141 |
0 |
0 |
T116 |
34551 |
262 |
0 |
0 |
T119 |
7721 |
71 |
0 |
0 |
T127 |
90642 |
201 |
0 |
0 |
T143 |
14579 |
62 |
0 |
0 |
T153 |
14139 |
19 |
0 |
0 |
T154 |
13594 |
21 |
0 |
0 |
T155 |
20573 |
48 |
0 |
0 |
T156 |
8985 |
90 |
0 |
0 |
T157 |
7876 |
7 |
0 |
0 |
T158 |
102367 |
811 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
4528 |
0 |
0 |
T116 |
34551 |
437 |
0 |
0 |
T119 |
7721 |
108 |
0 |
0 |
T127 |
90642 |
224 |
0 |
0 |
T143 |
14579 |
35 |
0 |
0 |
T153 |
14139 |
44 |
0 |
0 |
T154 |
13594 |
18 |
0 |
0 |
T155 |
20573 |
97 |
0 |
0 |
T156 |
8985 |
13 |
0 |
0 |
T157 |
7876 |
52 |
0 |
0 |
T158 |
102367 |
728 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
4321 |
0 |
0 |
T116 |
34551 |
312 |
0 |
0 |
T119 |
7721 |
87 |
0 |
0 |
T127 |
90642 |
193 |
0 |
0 |
T143 |
14579 |
21 |
0 |
0 |
T153 |
14139 |
6 |
0 |
0 |
T154 |
13594 |
16 |
0 |
0 |
T155 |
20573 |
39 |
0 |
0 |
T156 |
8985 |
51 |
0 |
0 |
T157 |
7876 |
36 |
0 |
0 |
T158 |
102367 |
687 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
3682 |
0 |
0 |
T116 |
34551 |
204 |
0 |
0 |
T119 |
7721 |
5 |
0 |
0 |
T127 |
90642 |
200 |
0 |
0 |
T143 |
14579 |
52 |
0 |
0 |
T153 |
14139 |
22 |
0 |
0 |
T154 |
13594 |
50 |
0 |
0 |
T155 |
20573 |
62 |
0 |
0 |
T156 |
8985 |
13 |
0 |
0 |
T157 |
7876 |
14 |
0 |
0 |
T158 |
102367 |
520 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
4068 |
0 |
0 |
T116 |
34551 |
214 |
0 |
0 |
T119 |
7721 |
46 |
0 |
0 |
T127 |
90642 |
227 |
0 |
0 |
T143 |
14579 |
36 |
0 |
0 |
T153 |
14139 |
25 |
0 |
0 |
T154 |
13594 |
27 |
0 |
0 |
T155 |
20573 |
45 |
0 |
0 |
T156 |
8985 |
16 |
0 |
0 |
T157 |
7876 |
26 |
0 |
0 |
T158 |
102367 |
743 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
4531 |
0 |
0 |
T104 |
18868 |
1 |
0 |
0 |
T116 |
34551 |
244 |
0 |
0 |
T119 |
7721 |
54 |
0 |
0 |
T127 |
90642 |
233 |
0 |
0 |
T143 |
14579 |
55 |
0 |
0 |
T153 |
14139 |
50 |
0 |
0 |
T154 |
13594 |
38 |
0 |
0 |
T155 |
20573 |
38 |
0 |
0 |
T156 |
8985 |
83 |
0 |
0 |
T157 |
7876 |
5 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
4143 |
0 |
0 |
T110 |
12140 |
3 |
0 |
0 |
T116 |
34551 |
213 |
0 |
0 |
T119 |
7721 |
92 |
0 |
0 |
T127 |
90642 |
269 |
0 |
0 |
T143 |
14579 |
54 |
0 |
0 |
T153 |
14139 |
86 |
0 |
0 |
T154 |
13594 |
12 |
0 |
0 |
T155 |
20573 |
112 |
0 |
0 |
T156 |
8985 |
38 |
0 |
0 |
T157 |
7876 |
10 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
4845 |
0 |
0 |
T116 |
34551 |
520 |
0 |
0 |
T119 |
7721 |
60 |
0 |
0 |
T127 |
90642 |
244 |
0 |
0 |
T143 |
14579 |
18 |
0 |
0 |
T153 |
14139 |
65 |
0 |
0 |
T154 |
13594 |
47 |
0 |
0 |
T155 |
20573 |
53 |
0 |
0 |
T156 |
8985 |
54 |
0 |
0 |
T157 |
7876 |
31 |
0 |
0 |
T158 |
102367 |
939 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
4349 |
0 |
0 |
T116 |
34551 |
349 |
0 |
0 |
T119 |
7721 |
97 |
0 |
0 |
T127 |
90642 |
221 |
0 |
0 |
T143 |
14579 |
47 |
0 |
0 |
T153 |
14139 |
86 |
0 |
0 |
T154 |
13594 |
28 |
0 |
0 |
T155 |
20573 |
99 |
0 |
0 |
T156 |
8985 |
13 |
0 |
0 |
T157 |
7876 |
22 |
0 |
0 |
T158 |
102367 |
787 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
4044 |
0 |
0 |
T116 |
34551 |
119 |
0 |
0 |
T119 |
7721 |
74 |
0 |
0 |
T127 |
90642 |
211 |
0 |
0 |
T143 |
14579 |
79 |
0 |
0 |
T153 |
14139 |
37 |
0 |
0 |
T154 |
13594 |
29 |
0 |
0 |
T155 |
20573 |
50 |
0 |
0 |
T156 |
8985 |
54 |
0 |
0 |
T157 |
7876 |
15 |
0 |
0 |
T158 |
102367 |
842 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
4449 |
0 |
0 |
T116 |
34551 |
348 |
0 |
0 |
T119 |
7721 |
48 |
0 |
0 |
T124 |
10522 |
84 |
0 |
0 |
T127 |
90642 |
206 |
0 |
0 |
T143 |
14579 |
123 |
0 |
0 |
T153 |
14139 |
40 |
0 |
0 |
T154 |
13594 |
29 |
0 |
0 |
T155 |
20573 |
84 |
0 |
0 |
T156 |
8985 |
55 |
0 |
0 |
T158 |
102367 |
891 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
4085 |
0 |
0 |
T116 |
34551 |
244 |
0 |
0 |
T119 |
7721 |
9 |
0 |
0 |
T127 |
90642 |
214 |
0 |
0 |
T143 |
14579 |
36 |
0 |
0 |
T153 |
14139 |
64 |
0 |
0 |
T154 |
13594 |
43 |
0 |
0 |
T155 |
20573 |
48 |
0 |
0 |
T156 |
8985 |
18 |
0 |
0 |
T157 |
7876 |
22 |
0 |
0 |
T158 |
102367 |
842 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
4527 |
0 |
0 |
T116 |
34551 |
275 |
0 |
0 |
T119 |
7721 |
3 |
0 |
0 |
T127 |
90642 |
223 |
0 |
0 |
T143 |
14579 |
41 |
0 |
0 |
T153 |
14139 |
48 |
0 |
0 |
T154 |
13594 |
52 |
0 |
0 |
T155 |
20573 |
46 |
0 |
0 |
T156 |
8985 |
29 |
0 |
0 |
T157 |
7876 |
45 |
0 |
0 |
T158 |
102367 |
823 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
1872 |
0 |
0 |
T116 |
34551 |
47 |
0 |
0 |
T119 |
7721 |
2 |
0 |
0 |
T127 |
90642 |
221 |
0 |
0 |
T143 |
14579 |
60 |
0 |
0 |
T153 |
14139 |
56 |
0 |
0 |
T154 |
13594 |
27 |
0 |
0 |
T155 |
20573 |
48 |
0 |
0 |
T156 |
8985 |
31 |
0 |
0 |
T157 |
7876 |
14 |
0 |
0 |
T158 |
102367 |
176 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
1869 |
0 |
0 |
T116 |
34551 |
97 |
0 |
0 |
T119 |
7721 |
13 |
0 |
0 |
T127 |
90642 |
209 |
0 |
0 |
T143 |
14579 |
27 |
0 |
0 |
T153 |
14139 |
33 |
0 |
0 |
T154 |
13594 |
30 |
0 |
0 |
T155 |
20573 |
83 |
0 |
0 |
T156 |
8985 |
21 |
0 |
0 |
T157 |
7876 |
6 |
0 |
0 |
T158 |
102367 |
160 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
1990 |
0 |
0 |
T116 |
34551 |
53 |
0 |
0 |
T119 |
7721 |
11 |
0 |
0 |
T124 |
10522 |
18 |
0 |
0 |
T127 |
90642 |
255 |
0 |
0 |
T143 |
14579 |
31 |
0 |
0 |
T153 |
14139 |
69 |
0 |
0 |
T154 |
13594 |
24 |
0 |
0 |
T155 |
20573 |
78 |
0 |
0 |
T156 |
8985 |
14 |
0 |
0 |
T158 |
102367 |
174 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
1915 |
0 |
0 |
T116 |
34551 |
44 |
0 |
0 |
T119 |
7721 |
5 |
0 |
0 |
T127 |
90642 |
223 |
0 |
0 |
T143 |
14579 |
69 |
0 |
0 |
T153 |
14139 |
23 |
0 |
0 |
T154 |
13594 |
68 |
0 |
0 |
T155 |
20573 |
54 |
0 |
0 |
T156 |
8985 |
14 |
0 |
0 |
T157 |
7876 |
12 |
0 |
0 |
T158 |
102367 |
193 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
2251 |
0 |
0 |
T116 |
34551 |
119 |
0 |
0 |
T119 |
7721 |
15 |
0 |
0 |
T127 |
90642 |
264 |
0 |
0 |
T143 |
14579 |
75 |
0 |
0 |
T153 |
14139 |
52 |
0 |
0 |
T154 |
13594 |
25 |
0 |
0 |
T155 |
20573 |
83 |
0 |
0 |
T156 |
8985 |
23 |
0 |
0 |
T157 |
7876 |
7 |
0 |
0 |
T158 |
102367 |
178 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
3650 |
0 |
0 |
T19 |
171765 |
0 |
0 |
0 |
T20 |
0 |
20 |
0 |
0 |
T32 |
0 |
57 |
0 |
0 |
T42 |
149887 |
0 |
0 |
0 |
T52 |
325591 |
9 |
0 |
0 |
T132 |
1208 |
0 |
0 |
0 |
T133 |
339286 |
0 |
0 |
0 |
T134 |
448599 |
0 |
0 |
0 |
T135 |
75928 |
0 |
0 |
0 |
T136 |
45395 |
0 |
0 |
0 |
T137 |
2549 |
0 |
0 |
0 |
T138 |
1020 |
0 |
0 |
0 |
T159 |
0 |
23 |
0 |
0 |
T160 |
0 |
22 |
0 |
0 |
T161 |
0 |
13 |
0 |
0 |
T162 |
0 |
39 |
0 |
0 |
T163 |
0 |
56 |
0 |
0 |
T164 |
0 |
11 |
0 |
0 |
T165 |
0 |
37 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
1871 |
0 |
0 |
T116 |
34551 |
64 |
0 |
0 |
T119 |
7721 |
8 |
0 |
0 |
T127 |
90642 |
198 |
0 |
0 |
T143 |
14579 |
30 |
0 |
0 |
T153 |
14139 |
55 |
0 |
0 |
T154 |
13594 |
41 |
0 |
0 |
T155 |
20573 |
42 |
0 |
0 |
T156 |
8985 |
14 |
0 |
0 |
T157 |
7876 |
3 |
0 |
0 |
T158 |
102367 |
153 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
1796 |
0 |
0 |
T116 |
34551 |
70 |
0 |
0 |
T119 |
7721 |
12 |
0 |
0 |
T127 |
90642 |
246 |
0 |
0 |
T143 |
14579 |
41 |
0 |
0 |
T153 |
14139 |
36 |
0 |
0 |
T154 |
13594 |
35 |
0 |
0 |
T155 |
20573 |
52 |
0 |
0 |
T156 |
8985 |
13 |
0 |
0 |
T157 |
7876 |
12 |
0 |
0 |
T158 |
102367 |
175 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
1729 |
0 |
0 |
T116 |
34551 |
54 |
0 |
0 |
T119 |
7721 |
7 |
0 |
0 |
T127 |
90642 |
196 |
0 |
0 |
T143 |
14579 |
42 |
0 |
0 |
T153 |
14139 |
62 |
0 |
0 |
T154 |
13594 |
49 |
0 |
0 |
T155 |
20573 |
73 |
0 |
0 |
T156 |
8985 |
25 |
0 |
0 |
T157 |
7876 |
37 |
0 |
0 |
T158 |
102367 |
86 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
1692 |
0 |
0 |
T116 |
34551 |
27 |
0 |
0 |
T119 |
7721 |
7 |
0 |
0 |
T127 |
90642 |
226 |
0 |
0 |
T143 |
14579 |
25 |
0 |
0 |
T153 |
14139 |
47 |
0 |
0 |
T154 |
13594 |
46 |
0 |
0 |
T155 |
20573 |
90 |
0 |
0 |
T156 |
8985 |
11 |
0 |
0 |
T157 |
7876 |
3 |
0 |
0 |
T158 |
102367 |
102 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
1667 |
0 |
0 |
T116 |
34551 |
37 |
0 |
0 |
T119 |
7721 |
7 |
0 |
0 |
T127 |
90642 |
214 |
0 |
0 |
T143 |
14579 |
21 |
0 |
0 |
T153 |
14139 |
68 |
0 |
0 |
T154 |
13594 |
38 |
0 |
0 |
T155 |
20573 |
84 |
0 |
0 |
T156 |
8985 |
22 |
0 |
0 |
T157 |
7876 |
18 |
0 |
0 |
T158 |
102367 |
122 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
1611 |
0 |
0 |
T116 |
34551 |
29 |
0 |
0 |
T119 |
7721 |
7 |
0 |
0 |
T127 |
90642 |
207 |
0 |
0 |
T143 |
14579 |
31 |
0 |
0 |
T153 |
14139 |
38 |
0 |
0 |
T154 |
13594 |
6 |
0 |
0 |
T155 |
20573 |
75 |
0 |
0 |
T156 |
8985 |
8 |
0 |
0 |
T157 |
7876 |
44 |
0 |
0 |
T158 |
102367 |
98 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
2299 |
0 |
0 |
T116 |
34551 |
96 |
0 |
0 |
T119 |
7721 |
21 |
0 |
0 |
T127 |
90642 |
227 |
0 |
0 |
T143 |
14579 |
66 |
0 |
0 |
T153 |
14139 |
40 |
0 |
0 |
T154 |
13594 |
29 |
0 |
0 |
T155 |
20573 |
58 |
0 |
0 |
T156 |
8985 |
33 |
0 |
0 |
T157 |
7876 |
5 |
0 |
0 |
T158 |
102367 |
284 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
1600 |
0 |
0 |
T116 |
34551 |
50 |
0 |
0 |
T119 |
7721 |
8 |
0 |
0 |
T127 |
90642 |
213 |
0 |
0 |
T143 |
14579 |
11 |
0 |
0 |
T153 |
14139 |
38 |
0 |
0 |
T154 |
13594 |
45 |
0 |
0 |
T155 |
20573 |
54 |
0 |
0 |
T156 |
8985 |
22 |
0 |
0 |
T157 |
7876 |
7 |
0 |
0 |
T158 |
102367 |
98 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
2503 |
0 |
0 |
T116 |
34551 |
93 |
0 |
0 |
T119 |
7721 |
25 |
0 |
0 |
T127 |
90642 |
218 |
0 |
0 |
T143 |
14579 |
35 |
0 |
0 |
T153 |
14139 |
23 |
0 |
0 |
T154 |
13594 |
29 |
0 |
0 |
T155 |
20573 |
63 |
0 |
0 |
T156 |
8985 |
37 |
0 |
0 |
T157 |
7876 |
26 |
0 |
0 |
T158 |
102367 |
357 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
1867 |
0 |
0 |
T116 |
34551 |
52 |
0 |
0 |
T119 |
7721 |
10 |
0 |
0 |
T127 |
90642 |
222 |
0 |
0 |
T143 |
14579 |
50 |
0 |
0 |
T153 |
14139 |
48 |
0 |
0 |
T154 |
13594 |
43 |
0 |
0 |
T155 |
20573 |
71 |
0 |
0 |
T156 |
8985 |
9 |
0 |
0 |
T157 |
7876 |
39 |
0 |
0 |
T158 |
102367 |
121 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
1732 |
0 |
0 |
T116 |
34551 |
42 |
0 |
0 |
T119 |
7721 |
19 |
0 |
0 |
T127 |
90642 |
236 |
0 |
0 |
T143 |
14579 |
26 |
0 |
0 |
T153 |
14139 |
54 |
0 |
0 |
T154 |
13594 |
46 |
0 |
0 |
T155 |
20573 |
57 |
0 |
0 |
T156 |
8985 |
5 |
0 |
0 |
T157 |
7876 |
33 |
0 |
0 |
T158 |
102367 |
98 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
1630 |
0 |
0 |
T116 |
34551 |
35 |
0 |
0 |
T119 |
7721 |
12 |
0 |
0 |
T127 |
90642 |
243 |
0 |
0 |
T143 |
14579 |
45 |
0 |
0 |
T153 |
14139 |
55 |
0 |
0 |
T154 |
13594 |
37 |
0 |
0 |
T155 |
20573 |
56 |
0 |
0 |
T156 |
8985 |
17 |
0 |
0 |
T157 |
7876 |
39 |
0 |
0 |
T158 |
102367 |
114 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
1602 |
0 |
0 |
T116 |
34551 |
29 |
0 |
0 |
T119 |
7721 |
6 |
0 |
0 |
T127 |
90642 |
203 |
0 |
0 |
T143 |
14579 |
31 |
0 |
0 |
T153 |
14139 |
22 |
0 |
0 |
T154 |
13594 |
39 |
0 |
0 |
T155 |
20573 |
46 |
0 |
0 |
T156 |
8985 |
16 |
0 |
0 |
T157 |
7876 |
13 |
0 |
0 |
T158 |
102367 |
107 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
1814 |
0 |
0 |
T116 |
34551 |
44 |
0 |
0 |
T119 |
7721 |
14 |
0 |
0 |
T127 |
90642 |
208 |
0 |
0 |
T143 |
14579 |
35 |
0 |
0 |
T153 |
14139 |
50 |
0 |
0 |
T154 |
13594 |
47 |
0 |
0 |
T155 |
20573 |
82 |
0 |
0 |
T156 |
8985 |
20 |
0 |
0 |
T157 |
7876 |
9 |
0 |
0 |
T158 |
102367 |
118 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
1906 |
0 |
0 |
T110 |
12140 |
8 |
0 |
0 |
T116 |
34551 |
37 |
0 |
0 |
T119 |
7721 |
4 |
0 |
0 |
T127 |
90642 |
204 |
0 |
0 |
T143 |
14579 |
44 |
0 |
0 |
T153 |
14139 |
54 |
0 |
0 |
T154 |
13594 |
42 |
0 |
0 |
T155 |
20573 |
99 |
0 |
0 |
T156 |
8985 |
21 |
0 |
0 |
T157 |
7876 |
46 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468509944 |
1620 |
0 |
0 |
T116 |
34551 |
41 |
0 |
0 |
T119 |
7721 |
11 |
0 |
0 |
T127 |
90642 |
224 |
0 |
0 |
T143 |
14579 |
10 |
0 |
0 |
T153 |
14139 |
67 |
0 |
0 |
T154 |
13594 |
30 |
0 |
0 |
T155 |
20573 |
16 |
0 |
0 |
T156 |
8985 |
7 |
0 |
0 |
T157 |
7876 |
46 |
0 |
0 |
T158 |
102367 |
122 |
0 |
0 |