Group : spi_device_env_pkg::tpm_read_hw_reg_cg_wrap::tpm_read_hw_reg_cg
Group Instance : tpm_access_0
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_access_0
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_access_0
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_access_1
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_access_1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_access_1
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_access_2
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_access_2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_access_2
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_access_3
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_access_3
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_access_3
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_access_4
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_access_4
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_access_4
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_did_vid
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_did_vid
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_did_vid
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_hash_start
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_hash_start
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_hash_start
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_int_enable
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_int_enable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_int_enable
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_int_status
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_int_status
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_int_status
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_int_vector
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_int_vector
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_int_vector
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_intf_capability
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_intf_capability
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_intf_capability
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_rid
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_rid
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_rid
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_sts
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_sts
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_sts
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
586 |
1 |
|
|
T4 |
6 |
|
T7 |
4 |
|
T15 |
2 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
572 |
1 |
|
|
T4 |
4 |
|
T91 |
8 |
|
T92 |
6 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
528 |
1 |
|
|
T4 |
4 |
|
T91 |
12 |
|
T92 |
12 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
588 |
1 |
|
|
T4 |
6 |
|
T7 |
4 |
|
T15 |
2 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
532 |
1 |
|
|
T4 |
4 |
|
T7 |
2 |
|
T91 |
10 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
2758 |
1 |
|
|
T4 |
30 |
|
T7 |
20 |
|
T15 |
4 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
2824 |
1 |
|
|
T4 |
18 |
|
T7 |
10 |
|
T15 |
8 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
2942 |
1 |
|
|
T4 |
24 |
|
T7 |
10 |
|
T17 |
6 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
2868 |
1 |
|
|
T4 |
24 |
|
T7 |
2 |
|
T15 |
2 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
2750 |
1 |
|
|
T4 |
18 |
|
T7 |
8 |
|
T15 |
12 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
6 |
1 |
|
|
T299 |
2 |
|
T214 |
2 |
|
T310 |
2 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
2832 |
1 |
|
|
T4 |
18 |
|
T7 |
6 |
|
T15 |
6 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
2468 |
1 |
|
|
T4 |
12 |
|
T7 |
14 |
|
T44 |
6 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |