Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4009319	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4529438

1

T1

12

T2

2744

T3

872

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4765959	1			T1	199		T2	181		T3	2
values[0x0]	1885185	1			T1	6		T2	1338		T3	443
values[0x1]	1887613	1			T1	5		T2	1317		T3	433

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2839820	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5698937

1

T1

74

T2

2769

T3

872

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	31048	1			T2	14		T5	9		T7	11
valid_sources[0x01]	40418	1			T1	5		T2	5		T5	3
valid_sources[0x02]	29864	1			T2	16		T4	6		T5	8
valid_sources[0x03]	31277	1			T2	13		T4	2		T5	9
valid_sources[0x04]	30651	1			T1	1		T2	8		T5	9
valid_sources[0x05]	29748	1			T2	18		T5	14		T6	9
valid_sources[0x06]	31366	1			T2	17		T4	1		T5	5
valid_sources[0x07]	36737	1			T1	2		T2	8		T3	16
valid_sources[0x08]	31698	1			T2	4		T5	1		T7	16
valid_sources[0x09]	34372	1			T2	15		T6	4		T7	1
valid_sources[0x0a]	30686	1			T1	6		T2	11		T4	1
valid_sources[0x0b]	35470	1			T2	17		T3	5		T5	2
valid_sources[0x0c]	31370	1			T2	19		T3	8		T7	3
valid_sources[0x0d]	33238	1			T2	10		T5	3		T7	28
valid_sources[0x0e]	31935	1			T1	1		T2	20		T3	6
valid_sources[0x0f]	31678	1			T2	14		T4	1		T5	6
valid_sources[0x10]	30237	1			T2	13		T5	4		T6	6
valid_sources[0x11]	32455	1			T2	9		T5	1		T6	13
valid_sources[0x12]	30537	1			T2	8		T5	7		T6	65
valid_sources[0x13]	31317	1			T2	9		T3	10		T5	7
valid_sources[0x14]	30997	1			T2	14		T5	9		T7	50
valid_sources[0x15]	33840	1			T2	17		T5	11		T6	1
valid_sources[0x16]	29857	1			T2	9		T3	22		T4	1
valid_sources[0x17]	33908	1			T2	13		T5	4		T6	26
valid_sources[0x18]	33218	1			T2	8		T3	6		T5	1
valid_sources[0x19]	36773	1			T1	3		T2	14		T3	11
valid_sources[0x1a]	39556	1			T2	11		T5	15		T7	49
valid_sources[0x1b]	29407	1			T2	8		T3	29		T4	2
valid_sources[0x1c]	32969	1			T2	10		T4	2		T6	19
valid_sources[0x1d]	30170	1			T2	5		T5	2		T6	1
valid_sources[0x1e]	31600	1			T2	14		T3	7		T5	16
valid_sources[0x1f]	34232	1			T2	8		T5	8		T6	55
valid_sources[0x20]	38666	1			T2	16		T5	7		T6	3
valid_sources[0x21]	33218	1			T2	17		T4	1		T5	13
valid_sources[0x22]	31556	1			T1	4		T2	8		T3	11
valid_sources[0x23]	32072	1			T1	3		T2	11		T3	10
valid_sources[0x24]	33873	1			T2	12		T4	2		T5	22
valid_sources[0x25]	29722	1			T2	9		T5	2		T6	11
valid_sources[0x26]	32149	1			T2	14		T6	5		T7	61
valid_sources[0x27]	30976	1			T2	12		T3	4		T4	1
valid_sources[0x28]	35332	1			T1	3		T2	11		T3	4
valid_sources[0x29]	34854	1			T1	2		T2	12		T3	5
valid_sources[0x2a]	31767	1			T1	1		T2	15		T5	10
valid_sources[0x2b]	29797	1			T2	2		T4	2		T5	4
valid_sources[0x2c]	30962	1			T2	9		T3	17		T4	2
valid_sources[0x2d]	30971	1			T2	4		T4	4		T5	1
valid_sources[0x2e]	33252	1			T1	9		T2	8		T3	13
valid_sources[0x2f]	30568	1			T2	10		T4	1		T5	3
valid_sources[0x30]	30110	1			T2	11		T4	1		T5	9
valid_sources[0x31]	32975	1			T2	18		T3	15		T4	3
valid_sources[0x32]	35577	1			T2	14		T3	4		T5	2
valid_sources[0x33]	33684	1			T2	13		T5	7		T6	1
valid_sources[0x34]	32827	1			T2	13		T3	3		T4	1
valid_sources[0x35]	30284	1			T2	11		T3	5		T5	1
valid_sources[0x36]	32644	1			T2	10		T5	14		T6	25
valid_sources[0x37]	36236	1			T1	3		T2	17		T5	6
valid_sources[0x38]	41796	1			T2	12		T5	7		T6	33
valid_sources[0x39]	29115	1			T2	15		T5	10		T7	14
valid_sources[0x3a]	30122	1			T2	14		T5	2		T6	9
valid_sources[0x3b]	33294	1			T2	6		T3	4		T4	1
valid_sources[0x3c]	30277	1			T2	10		T3	3		T5	10
valid_sources[0x3d]	45593	1			T1	1		T2	13		T4	1
valid_sources[0x3e]	34703	1			T2	9		T3	7		T5	4
valid_sources[0x3f]	32151	1			T1	1		T2	12		T4	1
valid_sources[0x40]	35503	1			T2	7		T5	3		T6	11
valid_sources[0x41]	30520	1			T2	18		T5	20		T6	1
valid_sources[0x42]	32304	1			T2	18		T5	1		T7	2
valid_sources[0x43]	33920	1			T2	7		T5	17		T6	17
valid_sources[0x44]	33982	1			T1	8		T2	7		T4	1
valid_sources[0x45]	28579	1			T2	13		T4	1		T5	17
valid_sources[0x46]	42071	1			T2	17		T3	13		T7	11
valid_sources[0x47]	31698	1			T2	11		T6	34		T8	9
valid_sources[0x48]	34348	1			T2	7		T5	9		T6	31
valid_sources[0x49]	33517	1			T1	2		T2	6		T4	1
valid_sources[0x4a]	32185	1			T2	14		T3	38		T5	11
valid_sources[0x4b]	29257	1			T2	12		T3	11		T5	1
valid_sources[0x4c]	30550	1			T2	12		T5	7		T8	8
valid_sources[0x4d]	32271	1			T2	5		T5	5		T8	10
valid_sources[0x4e]	31797	1			T2	6		T5	4		T7	25
valid_sources[0x4f]	50634	1			T2	9		T5	9		T6	26
valid_sources[0x50]	33009	1			T2	18		T5	2		T6	11
valid_sources[0x51]	31928	1			T2	17		T7	37		T8	5
valid_sources[0x52]	30977	1			T2	6		T4	2		T5	3
valid_sources[0x53]	32620	1			T1	5		T2	6		T3	30
valid_sources[0x54]	31772	1			T2	7		T5	1		T6	4
valid_sources[0x55]	30760	1			T2	3		T5	11		T7	1
valid_sources[0x56]	32084	1			T2	9		T5	11		T6	18
valid_sources[0x57]	34448	1			T2	14		T5	4		T6	2
valid_sources[0x58]	32543	1			T2	7		T3	9		T5	7
valid_sources[0x59]	33636	1			T2	12		T5	2		T6	6
valid_sources[0x5a]	33515	1			T1	10		T2	8		T5	2
valid_sources[0x5b]	31900	1			T2	13		T3	12		T5	12
valid_sources[0x5c]	31200	1			T2	8		T3	13		T5	25
valid_sources[0x5d]	34855	1			T1	2		T2	9		T5	3
valid_sources[0x5e]	34502	1			T2	12		T5	14		T6	8
valid_sources[0x5f]	30348	1			T2	8		T4	2		T5	4
valid_sources[0x60]	33858	1			T2	9		T3	30		T4	1
valid_sources[0x61]	33193	1			T2	9		T5	3		T7	44
valid_sources[0x62]	29722	1			T1	11		T2	13		T5	8
valid_sources[0x63]	33795	1			T2	8		T3	3		T5	4
valid_sources[0x64]	31460	1			T1	2		T2	12		T5	23
valid_sources[0x65]	33582	1			T2	17		T4	1		T5	11
valid_sources[0x66]	30908	1			T1	3		T2	9		T5	2
valid_sources[0x67]	36487	1			T2	10		T3	1		T5	9
valid_sources[0x68]	31112	1			T1	5		T2	12		T4	3
valid_sources[0x69]	33756	1			T2	17		T4	1		T6	15
valid_sources[0x6a]	30489	1			T2	6		T5	8		T6	11
valid_sources[0x6b]	36007	1			T2	7		T3	3		T5	9
valid_sources[0x6c]	31546	1			T2	11		T3	32		T5	9
valid_sources[0x6d]	32229	1			T1	3		T2	14		T3	11
valid_sources[0x6e]	34660	1			T1	2		T2	8		T3	8
valid_sources[0x6f]	32794	1			T2	6		T5	12		T6	1
valid_sources[0x70]	31520	1			T2	7		T3	12		T5	2
valid_sources[0x71]	34093	1			T2	9		T4	1		T5	4
valid_sources[0x72]	33085	1			T2	13		T5	22		T7	8
valid_sources[0x73]	32231	1			T2	11		T4	1		T5	4
valid_sources[0x74]	32992	1			T1	1		T2	10		T5	5
valid_sources[0x75]	34408	1			T2	9		T5	4		T6	30
valid_sources[0x76]	30920	1			T2	12		T5	9		T6	33
valid_sources[0x77]	30785	1			T1	2		T2	17		T3	2
valid_sources[0x78]	30376	1			T1	2		T2	22		T6	30
valid_sources[0x79]	33314	1			T2	12		T5	6		T6	21
valid_sources[0x7a]	36233	1			T1	1		T2	12		T4	1
valid_sources[0x7b]	32573	1			T2	10		T5	14		T6	35
valid_sources[0x7c]	32424	1			T2	13		T4	1		T5	24
valid_sources[0x7d]	30607	1			T2	8		T5	1		T6	1
valid_sources[0x7e]	33487	1			T2	3		T5	21		T6	35
valid_sources[0x7f]	32304	1			T2	17		T3	5		T7	27
valid_sources[0x80]	32675	1			T2	14		T3	46		T5	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1126012

1

T1

8

T2

103

T4

1

values[0x0]

all_enables

biggest_size

1713605

1

T1

4

T2

1334

T3

440

values[0x1]

all_enables

biggest_size

1689821

1

T2

1307

T3

432

T4

42