Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4028223

1

T1

198

T2

92

T3

6

full_word

4530512

1

T1

12

T2

2744

T3

872

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8558345	1			T1	210		T2	2836		T3	878
auto[TlIntgErrCmd]	127	1			T65	6		T101	9		T102	6
auto[TlIntgErrData]	112	1			T65	7		T101	6		T102	7
auto[TlIntgErrBoth]	151	1			T65	7		T101	5		T102	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4768950

1

T1

199

T2

181

T3

2

auto[1]

3789785

1

T1

11

T2

2655

T3

876

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3642516	1			T1	191		T2	78		T3	2
auto[TlIntgErrNone]	partial	auto[1]	385351	1			T1	7		T2	14		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	1126252	1			T1	8		T2	103		T4	1
auto[TlIntgErrNone]	full_word	auto[1]	3404226	1			T1	4		T2	2641		T3	872
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T65	3		T101	4		T102	3
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T65	3		T101	4		T102	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T115	1		T156	1		T170	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T101	1		T116	2		T168	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T65	4		T101	2		T102	4
auto[TlIntgErrData]	partial	auto[1]	55	1			T65	3		T101	2		T102	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T101	1		T115	1		T170	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T101	1		T171	1		T172	1
auto[TlIntgErrBoth]	partial	auto[0]	62	1			T65	2		T101	2		T102	1
auto[TlIntgErrBoth]	partial	auto[1]	76	1			T65	5		T101	3		T102	5
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T115	1		T170	1		T173	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T102	1		T115	1		T170	2